Abstract: A self-synchronous scrambler/descrambler and method for operating same are disclosed. A self-synchronous scrambler/descrambler comprises an M-bit Scrambler State memory for retaining M previously scrambled/descrambled bits, a SOP/EOP Zero Inserter for receiving replacing certain bytes of the bus word with a value of zero, a Mid-Packet Word Logic for scrambling/descrambling the received bits using the previously scrambled/descrambled bits from the M-bit Scrambler State memory; and a Barrel Shifter for rotating the M-bit Scrambler State memory backwards. The method for scrambling/descrambling bits, comprising receiving a bus word, replacing certain bytes of the bus word, scrambling/descrambling bits of the bus word by exclusive-ORing with previously scrambled/descrambled bits, retaining the scrambled/descrambled bits of the bus word; and rotating the scrambled/descrambled bits of the bus word backwards an amount.

Abstract: A multi-channel network device for interfacing between a plurality of physical data links and a control processor, where each physical data link is characterized by a data stream of data packets communicated according to a data link control protocol. The multi-channel network device includes a plurality of receive-side line interfaces, with each with each receive-side line interface having at least one channel associated therewith. Each receive-side line interface is operative to receive incoming data packets from one of the physical data links such that each incoming data packet is received in at least one incoming data segment. Each receive-side line interface is also operative to determine a time-slot number for each incoming data segment arriving thereon.