Abstract: An apparatus is provided for determining a configuration of memory modules. Each of the memory modules produces presence detect bits. In a first feature, the apparatus includes an external register for receiving the presence detect bits from the memory modules in parallel and a memory controller integrated circuit. The memory controller integrated circuit includes an internal register for storing the presence detect bits and logic circuitry for determining a memory configuration. The presence detect bits are serially transferred from the external register to the internal register. In a second feature, the logic circuitry for determining a memory configuration includes comparator circuitry for comparing the presence detect bits of each pair of memory modules and generating a match signal or a mismatch signal. When a match signal occurs, the presence detect bits of the memory module pair are loaded into a memory configuration register.

Abstract: A microprogrammed control unit of an information processing system having a control sequencer with dual microprogram counters for performing microdiagnostics simultaneously with performing macroprograms. The microdiagnostics comprise background and operability tests, the background tests being interleaved with macroinstruction operations under the control of the two independent microprogam counters. The background tests are run during processor idle time and the operability tests are executed at processor turn-on. The organization of the microdiagnostics into a hierarchical structure allows the use of the same microprogrammed test module for both the background and operability microdiagnostic tests. A prediction/residual coding technique provides fault detection for address and data information within the control sequencer.