Patents by Inventor Richard B. Irwin

Richard B. Irwin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10723618
    Abstract: An example microelectromechanical system (MEMS) switch comprises a hinge plane having two or more intersecting hinges; a switch plate; and a plurality of electrostatic pads. Selective activation of the electrostatic pads causes torsion of at least one of the two or more intersecting hinges to tilt the switch plate to a selected one of three or more positions.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: July 28, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Richard B. Irwin, Jr.
  • Publication number: 20180215612
    Abstract: An example microelectromechanical system (MEMS) switch comprises a hinge plane having two or more intersecting hinges; a switch plate; and a plurality of electrostatic pads. Selective activation of the electrostatic pads causes torsion of at least one of the two or more intersecting hinges to tilt the switch plate to a selected one of three or more positions.
    Type: Application
    Filed: October 23, 2015
    Publication date: August 2, 2018
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventor: Richard B. IRWIN, JR.
  • Publication number: 20130255741
    Abstract: An integrated circuit with an embedded heat exchanger for coupling heat to an embedded thermoelectric device from a thermal source that is electrically isolated from a thermoelectric device. A method for forming an integrated circuit with an embedded heat exchanger.
    Type: Application
    Filed: March 13, 2013
    Publication date: October 3, 2013
    Inventors: Henry L. Edwards, Richard B. Irwin, Tathagata Chatterjee
  • Patent number: 7902055
    Abstract: An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another embodiment of the invention is a method of manufacturing a Schottky diode 22 that includes providing a semiconductor substrate 3, forming a barrier layer 26 over the semiconductor substrate 3, forming a first metal layer 23 over the semiconductor substrate 3, annealing the semiconductor substrate 3 to form areas 24 of reacted first metal and areas 23 of un-reacted first metal, and removing selected areas 23 of the un-reacted first metal. The method further includes forming a second metal layer 30 over the semiconductor substrate 3 and annealing the semiconductor substrate 3 to form areas 28 of reacted second metal and areas 30 of un-reacted second metal.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: March 8, 2011
    Assignee: Texas Instruments Incoprorated
    Inventors: Richard B. Irwin, Tony T. Phan, Hong-Ryong Kim, Ming-Yeh Chuang, Jennifer S. Dumin, Patrick J. Jones, Fredric D. Bailey
  • Patent number: 7638415
    Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well (240) within a substrate (210) and forming a suppression implant (420) within the substrate (210). The method for manufacturing the zener diode may further include forming a cathode (620) and an anode (520) within the substrate (210), wherein the suppression implant (420) is located proximate the doped well (240) and configured to reduce threading dislocations.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: December 29, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Martin Mollat, Tathagata Chatterjee, Henry L. Edwards, Lance S. Robertson, Richard B. Irwin, Binghua Hu
  • Publication number: 20090061606
    Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well (240) within a substrate (210) and forming a suppression implant (420) within the substrate (210). The method for manufacturing the zener diode may further include forming a cathode (620) and an anode (520) within the substrate (210), wherein the suppression implant (420) is located proximate the doped well (240) and configured to reduce threading dislocations.
    Type: Application
    Filed: November 7, 2008
    Publication date: March 5, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: MARTIN MOLLAT, TATHAGATA CHATTERJEE, HENRY L. EDWARDS, LANCE S. ROBERTSON, RICHARD B. IRWIN, BINGHUA HU
  • Patent number: 7466009
    Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well within a substrate and forming a suppression implant within the substrate. The method for manufacturing the zener diode may further include forming a cathode and an anode within the substrate, wherein the suppression implant is located proximate the doped well and configured to reduce threading dislocations.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: December 16, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Martin Mollat, Tathagata Chatterjee, Henry L. Edwards, Lance S. Robertson, Richard B. Irwin, Binghua Hu
  • Publication number: 20070281433
    Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well within a substrate and forming a suppression implant within the substrate. The method for manufacturing the zener diode may further include forming a cathode and an anode within the substrate, wherein the suppression implant is located proximate the doped well and configured to reduce threading dislocations.
    Type: Application
    Filed: June 5, 2006
    Publication date: December 6, 2007
    Applicant: Texas Instruments Incorporated
    Inventors: Martin Mollat, Tathagata Chatterjee, Henry L. Edwards, Lance S. Robertson, Richard B. Irwin, Binghua Hu
  • Patent number: 6972470
    Abstract: An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another embodiment of the invention is a method of manufacturing a Schottky diode 22 that includes providing a semiconductor substrate 3, forming a barrier layer 26 over the semiconductor substrate 3, forming a first metal layer 23 over the semiconductor substrate 3, annealing the semiconductor substrate 3 to form areas 24 of reacted first metal and areas 23 of un-reacted first metal, and removing selected areas 23 of the un-reacted first metal. The method further includes forming a second metal layer 30 over the semiconductor substrate 3 and annealing the semiconductor substrate 3 to form areas 28 of reacted second metal and areas 30 of un-reacted second metal.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: December 6, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Richard B. Irwin, Tony T. Phan, Hong-Ryong Kim, Ming-Yeh Chuang, Jennifer S. Dumin, Patrick J. Jones, Fredric D. Bailey
  • Patent number: 6927174
    Abstract: A method for preparing a sample includes separating a portion of substrate from a sample, performing focused ion beam milling, and removing additional sample material using an etchant.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: August 9, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Adolfo Anciso, Patrick J. Jones, Richard B. Irwin