Patents by Inventor RICHARD B. O'CONNOR

RICHARD B. O'CONNOR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Processor core power event tracing
    Patent number: 10656697
    Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Tsvika Kurts, Beeman C. Strong, Richard B. O'Connor, Michael W. Chynoweth, Rajshree A. Chabukswar, Avner Lottem, Itamar Kazachinsky, Michael Mishaeli, Anthony Wojciechowski, Vikas R. Vasisht
  • Instruction and logic for interrupt and exception handling
    Patent number: 10445204
    Abstract: A processor includes a processor trace logical unit to produce branch execution records from execution of instructions. The processor further includes logic to determine that a condition has occurred on the processor during execution of the instructions. The condition is to include an asynchronous event or a return from a software handler for an asynchronous event. The processor further includes logic to determine whether event tracing is enabled for the processor. The processor also includes logic to generate a control flow event (CFE) packet. The CFE packet is to indicate a type of the condition. The processor further includes logic to generate an indicator of an instruction address that generated the condition.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Richard B. O'Connor, Beeman C. Strong, Michael W. Chynoweth, Rajshree A. Chabukswar
  • PROCESSOR CORE POWER EVENT TRACING
    Publication number: 20190050041
    Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.
    Type: Application
    Filed: March 5, 2018
    Publication date: February 14, 2019
    Inventors: Tsvika Kurts, Beeman C. Strong, Richard B. O'Connor, Michael W. Chynoweth, Rajshree A. Chabukswar, Avner Lottem, Itamar Kazachinsky, Michael Mishaeli, Anthony Wojciechowski, Vikas R. Vasisht
  • Processor core power event tracing
    Patent number: 9910475
    Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: March 6, 2018
    Assignee: Intel Corporation
    Inventors: Tsvika Kurts, Beeman C. Strong, Richard B. O'Connor, Michael W. Chynoweth, Rajshree A. Chabukswar, Avner Lottem, Itamar Kazachinsky, Michael Mishaeli, Anthony Wojciechowski, Vikas R. Vasisht
  • Instruction and Logic for Interrupt and Exception Handling
    Publication number: 20170090925
    Abstract: A processor includes a processor trace logical unit to produce branch execution records from execution of instructions. The processor further includes logic to determine that a condition has occurred on the processor during execution of the instructions. The condition is to include an asynchronous event or a return from a software handler for an asynchronous event. The processor further includes logic to determine whether event tracing is enabled for the processor. The processor also includes logic to generate a control flow event (CFE) packet. The CFE packet is to indicate a type of the condition. The processor further includes logic to generate an indicator of an instruction address that generated the condition.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: Richard B. O'Connor, Beeman C. Strong, Michael W. Chynoweth, Rajshree A. Chabukswar
  • PROCESSOR CORE POWER EVENT TRACING
    Publication number: 20160179166
    Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Inventors: TSVIKA KURTS, BEEMAN C. STRONG, RICHARD B. O'CONNOR, MICHAEL W. CHYNOWETH, RAJSHREE A. CHABUKSWAR, AVNER LOTTEM, ITAMAR KAZACHINSKY, MICHAEL MISHAELI, ANTHONY WOJCIECHOWSKI, VIKAS R. VASISHT