Abstract: A method for forming shallow low leakage ion implanted source/drain regions in an integrated circuit environment including semirecessed oxide isolation regions in which high parasitic device threshold voltages are provided by an oxidizing/annealing post implant process. Arsenic ions are implanted into a recessed oxide isolated substrate followed by a wet oxidation process and a non-oxidizing annealing process for a period of time to provide a passivating dielectric over low leakage source/drain regions of less than one micron junction depth and to provide adequate high temperature annealing to reduce the charge effects in the oxide isolation regions caused by the implanted arsenic ions.