Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.

Abstract: A lint filter assembly for removing lint and particulate matter from a clothes dryer exhaust system includes a conduit adapter and a filtering element. In a preferred embodiment the lint filter is a secondary filter removably connected inline between conduits substantially at the point of communication of the exhaust gases through a wall or floor to the outside, the filter portion not exceeding the conduit size in diameter.

Abstract: A lint filter assembly for removing lint and particulate matter from a clothes dryer exhaust system includes a conduit adapter and a filtering element. In a preferred embodiment the lint filter is a secondary filter removably connected inline between conduits substantially at the point of communication of the exhaust gases through a wall or floor to the outside, the filter portion not exceeding the conduit size in diameter.

Abstract: A lint filter assembly for removing lint and particulate matter from a clothes dryer exhaust system includes a conduit adapter and a filtering element. In a preferred embodiment the lint filter is a secondary filter removably connected inline between conduits substantially at the point of communication of the exhaust gases through a wall or floor to the outside, the filter portion not exceeding the conduit size in diameter.

Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.

Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.

Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.

Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A fast physical address is generated in parallel with a fully computed virtual-linear-physical address in a system using segmentation and optional paging. This fast physical address is used for a tentative or speculative memory reference, which reference can be canceled in the event the fast physical address does not match the fully computed address counterpart. In this manner, memory references can be accelerated in a computer system by avoiding a conventional translation scheme requiring two separate and sequential address translation operations—i.e. from virtual to linear, and from linear to physical.

Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.

Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.

Abstract: A data processing system which includes a memory and a processor comprising at least two execution units. The system further includes a microcode control unit for storing sequences of microinstructions and an execution microinstruction stack containing at least one stack frame containing the machine state of a first execution unit when the execution of a microinstruction has been interrupted. A memory microinstruction stack is provided to store a plurality of stack frames, stack frames being transferrable between the execution microinstruction stack and the memory microinstructiion stack. The microcode control unit contains sequences of monitor microinstructions and has associated with it a minotor microinstruction stack for storing the machine state of the first execution unit when the execution of a monitor microinstruction has been interrupted.

Abstract: Apparatus in a digital computer system capable of performing a call operation and a return operation for obtaining addresses of data from names representing the data. Each name is permanently associated with a procedure containing instructions to which the digital computer system responds. Each name further corresponds to a name table entry which is permanently associated with the same procedure. The corresponding name table entry for a name specifies how a base address and a displacement are to be derived using a plurality of current base addresses. The values of these addresses change only when the computer system executes a call operation suspending a current execution of a procedure and commencing another current execution or a return operation terminating the current execution and resuming the execution which was suspended to commence the terminated execution. The operation of resolving a name, i.e.

Abstract: A digital computer system having a memory system organized into procedure and data objects, each having a unique identifier code and an access control list, for storing items of information and a processor for processing data in response to instructions. The instructions contain operation codes and names representing data. Each name corresponds to a name table entry in a name table which contains information from which the processor determines the location and the format for the data. The name table entry specifies a base address of one of a set thereof which change value only when a call or a return instruction is executed. A name interpretation system fetches a name table entry, calculates the base address and a displacement using the name table entry and the current architectural base address and adds the base address to the displacement to form the address of the data represented by the name.

Abstract: A digital computer system including a memory and a processor. The memory operates in response to memory commands received from the processor. Items of data stored in the memory include instructions to which the processor responds. Each instruction contains an operation code which belongs to one of several sets of operation codes. The meaning of a given operation code is determined by the operation code set to which the instruction belongs. Some of the instructions also contain names representing items of data used in the operation specified by the operation code. The processor includes an operation code decoding system which decodes the operation code as required for the instruction set to which it belongs, a name resolution system for deriving the address of the data item represented by a name from the name using an architectural base address contained in the name resolution system, and a control system which controls the operation of the processor.

Abstract: A digital computer uses a memory which is structured into objects, which are blocks of storage of arbitrary length, in which data items are accessed by descriptors which for a desired data item specify the object, the offset into that object, and the length of the data object. The computer system of the present invention further provides the ability to execute any of a plurality of dialects of internal instructions, the repertoire of such dialects being virtually infinite, since there is the ability to load a supporting microcode during operation as needed.

Abstract: A digital data processing system has a memory organized into objects containing at least operands and instructions. Each object is identified by a unique and permanent identifier code which identifies the data processing system and the object. The system utilizes unique addressing mechanisms the addresses of which have object fields, offset fields and length fields for specifying the location and the total number of bits of an addressed object. The system uses a protection technique to prevent unauthorized access to objects by users who are identified by a subject number which identifies the user, a process of the system for executing the user's procedure, and the type of operation of the system to be performed by the user's procedure. An access control list for each object includes an access control list entry for each subject having access rights to the object and means for confirming that a particular active subject has access rights to a particular object before permitting access to the object.

Abstract: A digital data processing system has a memory organized into objects containing at least operands and instructions. Each object is identified by a unique and permanent identifier code which identifies the data processing system and the object. The system further uses multilevel microcode techniques for controlling sequences of microinstructions and for controlling the interval operations of the processor. The system uses a protection technique to prevent unauthorized access to objects by users who are identified by a subject number which identifies the user, a process of the system for executing a user's procedure, and the type of operation of the system to be performed by the user's procedure. An access control list for each object includes an access control list entry for each subject having access rights to the object and means for confirming that a particular active subject has access rights to a particular object before permitting access to the object.

Abstract: A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration.

Abstract: A method for executing call and return instructions in a digital computer system operating under control of microcode. The microcode may specify calls to and returns from sequences of microinstructions. A call microinstruction sequence corresponds to the call instruction. The call microcode in turn calls other microinstruction sequences for deriving pointers representing the location of the called procedure and of arguments from operands in the call instruction. As the call microcode obtains each argument pointer, it places the pointer on the stack. After it has obtained all of the argument pointers, it passes the pointer to the called procedure and a pointer to the argument pointers to a general call microinstruction sequence. That microinstruction sequence locates the called procedure, makes a new frame including the argument pointers, and saves the state necessary to resume execution of the call microinstruction sequence itself.

Abstract: A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information as objects and an extremely large address space accessible and common to all such systems.