Abstract: A method and system for performing dummy metal insertion in design data for an integrated circuit is disclosed, wherein the design data includes dummy metal objects inserted by a dummy fill tool. After a portion of the design data is changed, a check is performed to determine whether any dummy metal objects intersect with any other objects in the design data. If so, the intersecting dummy metal objects are deleted from the design data, thereby avoiding having to rerun the dummy fill tool.

Abstract: A method and system for optimizing a netlist change order flow is disclosed, wherein a design layout created by a layout tool using a reference netlist is to be changed by a modified version of the netlist, and wherein both netlists are hierarchical comprising. Aspects of the present invention include comparing the modified netlist with the original netlist outside of the layout tool, and automatically generating at least one change order based on differences found between the two netlists. After the change order is generated, the change order is then applied to the design layout to generate a modified design layout.

Abstract: A method of implementing an engineering change order includes steps of: (a) receiving as input an integrated circuit design; (b) receiving as input an engineering change order to the integrated circuit design; (c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; (d) performing a routing of the integrated circuit design that excludes routing of any net that is not enclosed by the window; (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and (f) generating as output the revised integrated circuit design.

Abstract: A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit design to verify compliance with a set of design rules; (b) generating a results database of design rule violations detected by the physical design validation; (c) identifying locations in the integrated circuit design from the results database for making design corrections according to a post-processing rule deck so that the locations of the design corrections comply with the set of design rules; and (d) implementing the design corrections in the integrated circuit design.

Abstract: A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit design to verify compliance with a set of design rules; (b) generating a results database of design rule violations detected by the physical design validation; (c) identifying locations in the integrated circuit design from the results database for making design corrections according to a post-processing rule deck so that the locations of the design corrections comply with the set of design rules; and (d) implementing the design corrections in the integrated circuit design.

Abstract: A tool and method for implementing engineering change orders. The tool and method provides that a change file is checked, equivalent engineering change orders are computed and applied to an active cell. The engineering change orders are registered with a pre-determined tool name, and it is detected and reported if another tool needs to be run to restore routing information. The active cell is not automatically saved after the engineering change orders are applied. Instead, a user must manually save the active cell after the tool is run. The tool can work with three different name spaces: Verilog, VHDL and Avant! Verilog.

Abstract: A method and computer program product for verifying an incremental change to an integrated circuit design are described that include steps of: (a) receiving as input an integrated circuit design database; (b) receiving as input an engineering change order; (c) identifying and marking objects in the integrated circuit design database to indicate a current state of the integrated circuit design database; (d) applying the engineering change order to the integrated circuit design database; (e) analyzing the integrated circuit design database to generate a list of incremental changes to the integrated circuit design database resulting from the engineering change order; (f) identifying and marking objects in the integrated circuit design database included in the list of incremental changes to distinguish objects in the integrated circuit design database that were changed from the current state; and (g) streaming out the integrated circuit design database.

Abstract: A method of partitioning an integrated circuit design for physical design verification includes steps of: (a) receiving as input a representation of an integrated circuit design having a number of physical design layers; (b) receiving as input a composite run deck specifying rule checks to be performed on the integrated circuit design; (c) partitioning the composite run deck into partitioned run decks so that the number of physical design layers referenced by each of the partitioned run decks is a minimum; (d) parsing the representation of the integrated circuit design to filter only the physical design layers required for each of the partitioned run decks into a filtered data deck for each of the partitioned run decks; and (e) generating as output the filtered data deck for each of the partitioned run decks.

Abstract: A method and system for optimizing a netlist change order flow is disclosed, wherein a design layout created by a layout tool using a reference netlist is to be changed by a modified version of the netlist, and wherein both netlist are hierarchical comprising. Aspects of the present invention include comparing the modified netlist with the original netlist outside of the layout tool, and automatically generating at least one change order based on differences found between the two netlists. After the change order is generated, the change order is then applied to the design layout to generate a modified design layout.

Abstract: A method and system for performing dummy metal insertion in design data for an integrated circuit is disclosed, wherein the design data includes dummy metal objects inserted by a dummy fill tool. After a portion of the design data is changed, a check is performed to determine whether any dummy metal objects intersect with any other objects in the design data. If so, the intersecting dummy metal objects are deleted from the design data, thereby avoiding having to rerun the dummy fill tool.

Abstract: A tool and method for implementing engineering change orders. The tool and method provides that a change file is checked, equivalent engineering change orders are computed and applied to an active cell. The engineering change orders are registered with a pre-determined tool name, and it is detected and reported if another tool needs to be run to restore routing information. The active cell is not automatically saved after the engineering change orders are applied. Instead, a user must manually save the active cell after the tool is run. The tool can work with three different name spaces: Verilog, VHDL and Avant! Verilog.