Abstract: In various embodiments, a first and second complex multiplier may be configured to receive an input signal and provide a baseband I component signal and a baseband Q component signal, respectively. A first and second filter may be configured to filter the baseband I component signal and the baseband Q component signal, respectively. An equalizer may be configured to equalize the filtered baseband I component signal and the filtered baseband Q component signal. A carrier recovery portion may be configured to generate a reference signal based on the equalized filtered baseband I component signal and the equalized filtered baseband Q component signal. A first and second multilevel comparator may be configured to receive the equalized filtered baseband I component signal from the carrier recovery portion and provide an output I and receive the equalized filtered baseband Q component signal and provide an output Q signal for further modulation.

Abstract: In various embodiments, a first and second complex multiplier may be configured to receive an input signal and provide a baseband I component signal and a baseband Q component signal, respectively. A first and second filter may be configured to filter the baseband I component signal and the baseband Q component signal, respectively. An equalizer may be configured to equalize the filtered baseband I component signal and the filtered baseband Q component signal. A carrier recovery portion may be configured to generate a reference signal based on the equalized filtered baseband I component signal and the equalized filtered baseband Q component signal. A first and second multilevel comparator may be configured to receive the equalized filtered baseband I component signal from the carrier recovery portion and provide an output I and receive the equalized filtered baseband Q component signal and provide an output Q signal for further modulation.

Abstract: A radio frequency receiver comprising a receiver module, an intermediate frequency (“IF”) module, a synthesizer module and a controller module. The receiver module receives a radio frequency signal and provides a baseband in-phase signal and a baseband quadrature signal, eliminates a sideband of the in-phase and quadrature signals to create a first and a second signal, downconverts the first and second signal to a first and a second IF signal, and selects one of the first or second IF signals. The IF module receives the first or second IF signal, performs analog-to-digital conversion on the first or second IF signal, and demodulates the digitally converted IF signal. The synthesizer module receives a programmable reference signal, downconverts the reference signal to an IF feedback signal, downconverts the reference signal to a baseband feedback signal, provides the IF feedback signal to the IF module, and provides the baseband feedback signal to the receiver module.

Abstract: A radio frequency receiver comprising a receiver module, an intermediate frequency (“IF”) module, a synthesizer module and a controller module. The receiver module receives a radio frequency signal and provides a baseband in-phase signal and a baseband quadrature signal, eliminates a sideband of the in-phase and quadrature signals to create a first and a second signal, downconverts the first and second signal to a first and a second IF signal, and selects one of the first or second IF signals. The IF module receives the first or second IF signal, performs analog-to-digital conversion on the first or second IF signal, and demodulates the digitally converted IF signal. The synthesizer module receives a programmable reference signal, downconverts the reference signal to an IF feedback signal, downconverts the reference signal to a baseband feedback signal, provides the IF feedback signal to the IF module, and provides the baseband feedback signal to the receiver module.

Abstract: In various embodiments, a first and second complex multiplier may be configured to receive an input signal and provide a baseband I component signal and a baseband Q component signal, respectively. A first and second filter may be configured to filter the baseband I component signal and the baseband Q component signal, respectively. An equalizer may be configured to equalize the filtered baseband I component signal and the filtered baseband Q component signal. A carrier recovery portion may be configured to generate a reference signal based on the equalized filtered baseband I component signal and the equalized filtered baseband Q component signal. A first and second multilevel comparator may be configured to receive the equalized filtered baseband I component signal from the carrier recovery portion and provide an output I and receive the equalized filtered baseband Q component signal and provide an output Q signal for further modulation.

Abstract: In various embodiments, a first and second complex multiplier may be configured to receive an input signal and provide a baseband I component signal and a baseband Q component signal, respectively. A first and second filter may be configured to filter the baseband I component signal and the baseband Q component signal, respectively. An equalizer may be configured to equalize the filtered baseband I component signal and the filtered baseband Q component signal. A carrier recovery portion may be configured to generate a reference signal based on the equalized filtered baseband I component signal and the equalized filtered baseband Q component signal. A first and second multilevel comparator may be configured to receive the equalized filtered baseband I component signal from the carrier recovery portion and provide an output I and receive the equalized filtered baseband Q component signal and provide an output Q signal for further modulation.

Abstract: In various embodiments, a first and second complex multiplier may be configured to receive an input signal and provide a baseband I component signal and a baseband Q component signal, respectively. A first and second filter may be configured to filter the baseband I component signal and the baseband Q component signal, respectively. An equalizer may be configured to equalize the filtered baseband I component signal and the filtered baseband Q component signal. A carrier recovery portion may be configured to generate a reference signal based on the equalized filtered baseband I component signal and the equalized filtered baseband Q component signal. A first and second multilevel comparator may be configured to receive the equalized filtered baseband I component signal from the carrier recovery portion and provide an output I and receive the equalized filtered baseband Q component signal and provide an output Q signal for further modulation.

Abstract: A system and method of switching from a first receiver receiving a constant bit rate signal to a second receiver receiving the constant bit rate signal, where the constant bit rate signal received by the first and second receivers is converted to a first baseband signal and a second baseband signal comprising estimating a signal quality metric of the first baseband signal, comparing the signal quality metric to a predetermined threshold, and switching from the first baseband signal to the second baseband signal if the signal quality metric is greater than the threshold.

Abstract: A radio frequency receiver comprising a receiver module, an intermediate frequency (“IF”) module, a synthesizer module and a controller module. The receiver module receives a radio frequency signal and provides a baseband in-phase signal and a baseband quadrature signal eliminates a sideband of the in-phase and quadrature signals to create a first and a second signal, downconverts the first and second signal to a first and a second IF signal, and selects one of the first or second IF signals. The IF module receives the first or second IF signal, performs analog-to-digital conversion on the first or second IF signal, and demodulates the digitally converted. If signal The synthesizer module receives a programmable reference signal, downconverts the reference signal to an IF feedback signal, downconverts the reference signal to a baseband feedback signal provides the IF feedback signal to the IF module, and provides the baseband feedback signal to the receiver module.

Abstract: A system and method of switching from a first receiver receiving a constant bit rate signal to a second receiver receiving the constant bit rate signal, where the constant bit rate signal received by the first and second receivers is converted to a first baseband signal and a second baseband signal comprising estimating a signal quality metric of the first baseband signal, comparing the signal quality metric to a predetermined threshold, and switching from the first baseband signal to the second baseband signal if the signal quality metric is greater than the threshold.

Abstract: A gateless digital circuit and method for generating a second clock with a frequency of N/M of the frequency of a first clock, wherein N and M are integers, N?M/2. The gateless digital circuit having a modulo M function, a register and a adder operable connected to generate the second clock, where both N and M are independently selectable.

Abstract: A gateless digital circuit and method for generating a second clock with a frequency of N/M of the frequency of a first clock, wherein N and M are integers, N?M/2. The gateless digital circuit having a modulo M function, a register and a adder operable connected to generate the second clock, where both N and M are independently selectable.

Abstract: A reduced phase error derotator (100) includes a novel phase accumulator (12), which provides an output signal (38) having a value which approaches zero when the value of the phase accumulator input signal (34) is zero. This is particularly advantageous in situations wherein a sudden phase transient appears at the input of the phase accumulator (12) causing the phase accumulator input signal (34) to become nonzero, the phase accumulator (12) will quickly react to this transient, resulting in the value of the phase accumulator output signal (38) to be nonzero. When the transient at the input to the phase accumulator (12) disappears and the value of the phase accumulator input signal (34) returns to zero, the phase accumulator (12) will quickly react to this change resulting in the value of the phase accumulator output signal (38) becoming zero.

Abstract: A decision directed frequency detector and method for a quadrature amplitude modulated signal (QAM) demodulator. The demodulator interacts with a voltage controlled oscillator (VCO) that generates a carrier signal to demodulate the QAM signal into a baseband signal. The frequency detector determines the direction of rotation of the baseband signal by sampling the baseband signal relative to predetermined points in the phase plane. For example, if one sample has a negative phase offset with respect to a predetermined point and the next one has a positive phase offset, it detects that the rotation is clockwise, and vice-versa. A control signal is supplied to the VCO and the frequency of the carrier signal is adjusted to stop the rotation of the baseband signal.

Abstract: A system and method for synchronizing a hub radio and a remote radio by initially changing the frequency of the remote radio by a predetermined frequency offset, and then stepwise changing the frequency as a function of the tolerance of the hub radio to synchronize.

Abstract: A receiver includes a demodulator and a false carrier lock detector circuit for a quadrature amplitude modulated (QAM) signal. The demodulator includes a controllable oscillator and an offset frequency generator for generating an offset frequency for the controllable oscillator to lock to a carrier of the QAM signal. The demodulator is susceptible to false carrier locking responsive to the offset frequency being substantially equal to the symbol rate divided by four or an integer multiple thereof. The receiver further includes the false carrier lock detector circuit including a first detector for detecting consecutive symbols spaced 180.degree. apart, and a second detector for determining whether an intervening sample between the consecutive symbols is outside a predetermined distance from the origin. The first and second detectors cooperate to determine false carrier locking based upon the intervening sample being outside a predetermined distance from the origin.

Abstract: A device and method for detecting a fault in a cable while the cable is in use. A low frequency analog test signal is added to the signal normally sent across the cable under test. Under normal operating conditions the test signal does not reflect from the load which terminates the cable. Under fault conditions, the test signal is reflected and is detected by an analog test signal detector.