Abstract: A method of, shared register system and system for controlling access to a register are described. The shared register stores a plurality of bits including control and data bits. An access signal and a combined signal including a control portion and a data portion are received and the data portion of the combined signal is written to one or more data bits of the shared register corresponding to the control portion of the combined signal. A shared register system for controlling access to portions of a shared register includes a register having storage for bits and a register access control configured to receive an access signal and a combined signal. The register access control is operatively connected with the register to control write access to the register based on the access signal and the control portion of the combined signal.

Abstract: A computer-implemented method of generating timeout errors based on shared register access by two processors is described. A processor access timer is started responsive to generation of an access request by a first processor. The generated first processor access request is transmitted to a shared storage component including a shared register and able to communicate with both the first and second processors. A timeout error is generated responsive to the processor access timer exceeding a processor predetermined timeout threshold value.

Abstract: A generic interface for a module, method of providing a generic interface, and a module controller system providing a register slave having a generic interface are described. The interface includes an addressable interface, a control interface, and a module interface configured to interact with two or more module configurations. The interface has multiple operating modes at least one of which includes a monitor mode. The method includes receiving an address from a register master identifying the module address to be monitored, reading the received module address content from the module, and transmitting the read content to the monitor port. The system includes a register master, a register slave connected with the register master and adapted to connect with the module, and a monitor port connected with the register slave to receive the monitored module address contents.

Abstract: A computer-implemented method of generating timeout errors based on shared register access by two processors is described. A processor access timer is started responsive to generation of an access request by a first processor. The generated first processor access request is transmitted to a shared storage component including a shared register and able to communicate with both the first and second processors. A timeout error is generated responsive to the processor access timer exceeding a processor predetermined timeout threshold value.

Abstract: A system for interfacing a processor with a peripheral component. The system includes a module interface connected with the processor, a peripheral interface unit connected between the module interface and a peripheral component connected to the peripheral interface unit. The peripheral interface unit includes a peripheral interface to communicate with a peripheral component, a mailbox storage unit to store data defining communication between the module interface and the peripheral interface, and an interface state machine to communicate data between the mailbox storage unit and the peripheral interface responsive to commands received from the module interface and the peripheral interface.

Abstract: In an embodiment of the invention, a method for providing security to an account, includes: providing a code; validating the code; if the code is an access code for accessing an account, then permitting transactions on the account if the access code is valid; and if the code is an alarm password associated with the account, then preventing transactions on the account if the alarm password is valid. Another embodiment of the invention provides an apparatus or system that can perform the above method.

Abstract: A method of, shared register system and system for controlling access to a register are described. The shared register stores a plurality of bits including control and data bits. An access signal and a combined signal including a control portion and a data portion are received and the data portion of the combined signal is written to one or more data bits of the shared register corresponding to the control portion of the combined signal. A shared register system for controlling access to portions of a shared register includes a register having storage for bits and a register access control configured to receive an access signal and a combined signal. The register access control is operatively connected with the register to control write access to the register based on the access signal and the control portion of the combined signal.