Abstract: In one embodiment, a method includes receiving at a thermal modeling module, data from a Power Sourcing Equipment device (PSE) for cables extending from the PSE to Powered Devices (PDs), the cables configured to transmit power and data from the PSE to the PDs, calculating at the thermal modeling module, thermal characteristics for the cables based on the data, and identifying a thermal rise above a specified threshold at one of the cables. The data comprises real-time electrical data for the cables. An apparatus and logic are also disclosed herein.

Abstract: In one embodiment, a method includes receiving at a thermal modeling module, data from a Power Sourcing Equipment device (PSE) for cables extending from the PSE to Powered Devices (PDs), the cables configured to transmit power and data from the PSE to the PDs, calculating at the thermal modeling module, thermal characteristics for the cables based on the data, and identifying a thermal rise above a specified threshold at one of the cables. The data comprises real-time electrical data for the cables. An apparatus and logic are also disclosed herein.

Abstract: A family of minimally cross-hybridizing nucleotide sequences, methods of use, etc. A specific family of 210 24mers is described.

Abstract: A family of minimally cross-hybridizing nucleotide sequences, methods of use, etc. A specific family of 210 24mers is described.

Abstract: Methods of forming a gate dielectric layer, and a composite gate dielectric layer, for a thin film transistor, has been developed. A first embodiment of this invention describes the procedure used to create the composite gate dielectric layer. A first, thin silicon oxide gate dielectric layer is thermally grown on an underlying active semiconductor layer, such as polysilicon. A first anneal procedure, is performed at a temperature greater than the temperature used for the thermal growth of this layer, resulting in improved parametric integrity. A thicker, second silicon oxide gate dielectric layer is then thermally deposited, followed by an anneal procedure used to provide a composite gate dielectric layer comprised of a densified, thermally deposited second silicon oxide gate dielectric layer, on an underlying, thermally grown first silicon oxide gate dielectric layer.

Abstract: A family of minimally cross-hybridizing nucleotide sequences, methods of use, etc. A specific family of 210 24mers is described.

Abstract: A liquid crystal display device is described in which the TFTs are located directly below the spaces between pixels. The black matrix comprises an array of opaque conductive elements with one such element being above each TFT. The black matrix is incorporated into the TFT structure. By using highly conductive material for the black matrix elements their thickness is held to a minimum, thereby minimizing their impact on planarity. Optionally, this highly conductive layer may be laminated with layers of a non-reflective conductor that makes good ohmic contact to silicon. In one embodiment, metal filled via holes are added that connect the TFTs to the transparent conductive pixel control elements by way of the black matrix layer. In another embodiment, the black matrix layer is connected to be in parallel with the gate electrode, thereby reducing the series resistance of the latter. A process for manufacturing the display is also described.

Abstract: Methods of forming a gate dielectric layer, and a composite gate dielectric layer, for a thin film transistor, has been developed. A first embodiment of this invention describes the procedure used to create the composite gate dielectric layer. A first, thin silicon oxide gate dielectric layer is thermally grown on an underlying active semiconductor layer, such as polysilicon. A first anneal procedure, is performed at a temperature greater than the temperature used for the thermal growth of this layer, resulting in improved parametric integrity. A thicker, second silicon oxide gate dielectric layer is then thermally deposited, followed by an anneal procedure used to provide a composite gate dielectric layer comprised of a densified, thermally deposited second silicon oxide gate dielectric layer, on an underlying, thermally grown first silicon oxide gate dielectric layer.