Patents by Inventor Richard Burch

Richard Burch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210142122
    Abstract: Classifying wafers using Collaborative Learning. An initial wafer classification is determined by a rule-based model. A predicted wafer classification is determined by a machine learning model. Multiple users can manually review the classifications to confirm or modify, or to add user classifications. All of the classifications are input to the machine learning model to continuously update its scheme for detection and classification.
    Type: Application
    Filed: October 14, 2020
    Publication date: May 13, 2021
    Applicant: PDF Solutions, Inc.
    Inventors: Tomonori Honda, Richard Burch, John Kibarian, Lin Lee Cheong, Qing Zhu, Vaishnavi Reddipalli, Kenneth Harris, Said Akar, Jeffrey D David, Michael Keleher, Brian Stein, Dennis Ciplickas
  • Publication number: 20210118754
    Abstract: A machine learning model for each die for imputing process control parameters at the die. The model is based on wafer sort parametric measurements at multiple test sites across the entire wafer, as well as yield results for the wafer. This allows for a better analysis of outlier spatial patterns leading to improved yield results.
    Type: Application
    Filed: October 16, 2020
    Publication date: April 22, 2021
    Applicant: PDF Solutions, Inc.
    Inventors: Richard Burch, Qing Zhu, Jonathan Holt
  • Publication number: 20210117861
    Abstract: A sequence of models accumulates r-squared values for an increasing number of variables in order to quantify the importance of each variable to the prediction of a targeted yield or parametric response.
    Type: Application
    Filed: October 16, 2020
    Publication date: April 22, 2021
    Applicant: PDF Solutions, Inc.
    Inventors: Richard Burch, Qing Zhu, Jonathan Holt, Tomonori Honda
  • Publication number: 20210103489
    Abstract: Scheme for detection and classification of semiconductor equipment faults. Sensor traces are monitored and processed to separate known abnormal operating conditions from unknown abnormal operating conditions. Feature engineering permits focus on relevant traces for a targeted feature. A machine learning model is built to detect and classify based on an initial classification set of anomalies. The machine learning model is continuously updated as more traces are processed and learned.
    Type: Application
    Filed: October 6, 2020
    Publication date: April 8, 2021
    Applicant: PDF Solutions, Inc.
    Inventors: Richard Burch, Jeffrey D. David, Qing Zhu, Tomonori Honda, Lin Lee Cheong
  • Patent number: 10656204
    Abstract: Disclosed is a system and method for collecting trace data of integrated circuits from the back-end assembly tools and using yield, reliability, and burn-in data to distinguish good circuit traces from bad ones. Described further is an system and method for implementing a heuristic mapping of trace data for distinguishing between good or bad traces in an Internet-based or offline application. The result of this detection can then be used for yield improvement or for burn-in reduction where for example burn-in chips having “good” circuit traces are subjected to thermal stress for less time than for chips identified as having “bad” circuit traces.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: May 19, 2020
    Assignee: PDF Solutions, Inc.
    Inventors: Brian Stine, Richard Burch, Nobuchika Akiya
  • Publication number: 20190146032
    Abstract: Disclosed is a system and method for collecting trace data of integrated circuits from the back-end assembly tools and using yield, reliability, and burn-in data to distinguish good circuit traces from bad ones. Described further is an system and method for implementing a heuristic mapping of trace data for distinguishing between good or bad traces in an Internet-based or offline application. The result of this detection can then be used for yield improvement or for burn-in reduction where for example burn-in chips having “good” circuit traces are subjected to thermal stress for less time than for chips identified as having “bad” circuit traces.
    Type: Application
    Filed: September 21, 2018
    Publication date: May 16, 2019
    Inventors: Brian Stine, Richard Burch, Nobuchika Akiya
  • Patent number: 10268562
    Abstract: Described is a method of reducing multitudes of input data signals to a manageable plurality of input data signals and using the manageable plurality of input data signals to obtain response data that is provided to the semiconductor wafer, packaging, or design facility.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: April 23, 2019
    Assignee: PDF Solutions, Inc.
    Inventors: Brian Stine, Richard Burch, Lijin Zhu
  • Patent number: 7515591
    Abstract: A data transmission scheduler subsystem for a multi-channel bank communication system architecture contains a plurality of ‘per port’ schedulers. Each per port scheduler is resident in the system's primary channel bank, and is operative to controllably cause customer-destined data, that has been buffered from a communication network into switch fabric storage circuitry of the primary channel bank, to be controllably read out for downlink transmission to associated destination data ports of the channel banks at the destination data ports' data rates.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: April 7, 2009
    Assignee: Adtran, Inc.
    Inventors: Richard A. Burch, Neil M. Jensen, Dennis B. McMahan, Timothy David Rochell
  • Patent number: 7477596
    Abstract: A policing engine for use in a telecommunication equipment shelf is operative to control the rate at which customer-sourced ATM packets are passed to buffers associated with different classes of service to which customers may subscribe. The policing engine examines the rate at which ATM cells are supplied to it from the line card ports, whether the cells are AAL5 cells, and how full are the buffers into which the cells are to be written. If cells are supplied to the policing engine at a rate faster than prescribed peak or sustained cell rates, or if the cell buffer begins to fill up, the policing engine controllably discards incoming cells, thereby effectively ‘throttling’ the cell flow rate through it.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: January 13, 2009
    Assignee: Adtran, Inc.
    Inventors: Richard A. Burch, Neil M. Jensen, Dennis B. McMahan, Timothy David Rochell
  • Patent number: 7433365
    Abstract: A single switch fabric-based, multi-channel bank digital subscriber line access multiplexer includes a master channel bank containing a master switch module in which the switch fabric and a downstream-directed traffic scheduler reside, and one or more expansion channel banks that are linked with the master channel bank by way of upstream and downstream communication links. Distributed among the channel banks are respective policing mechanisms and cell rate control mechanisms that control upstream-directed communications from line card ports of each expansion channel bank to the switch fabric. Downstream data transmissions are locked to network timing, and are scheduled by a centralized scheduling mechanism resident in the master channel bank.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: October 7, 2008
    Assignee: Adtran, Inc.
    Inventors: Richard A. Burch, Neil M. Jensen, Dennis B. McMahan, Timothy David Rochell, Robert James Toth
  • Patent number: 7415386
    Abstract: A method for analyzing a sample of wafers includes identifying F failure metrics applicable to at least one pattern on each wafer within the sample. Z spatial and/or reticle zones are identified on each wafer, where Z and F are integers. Values are provided for each failure metric, for each zone on each wafer. A point is defined for each respective wafer in an N-dimensional space, where N=F*Z, and each point has coordinates corresponding to values of the F failure metrics in each of the zones of the corresponding wafer. The sample of wafers is partitioned into a plurality of clusters, so that the wafers within each clusters are close to each other in the N-dimensional space. A plurality of clusters is thus identified from the sample of wafers so that within each individual cluster, the wafers have similar defects to each other.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: August 19, 2008
    Assignee: PDF Solutions, Inc.
    Inventors: Richard Burch, Paul Lin, Spencer Graves, Eric Antonissen
  • Publication number: 20070288185
    Abstract: A method for analyzing a sample of wafers includes identifying F failure metrics applicable to at least one pattern on each wafer within the sample. Z spatial and/or reticle zones are identified on each wafer, where Z and F are integers. Values are provided for each failure metric, for each zone on each wafer. A point is defined for each respective wafer in an N-dimensional space, where N=F*Z, and each point has coordinates corresponding to values of the F failure metrics in each of the zones of the corresponding wafer. The sample of wafers is partitioned into a plurality of clusters, so that the wafers within each clusters are close to each other in the N-dimensional space. A plurality of clusters is thus identified from the sample of wafers so that within each individual cluster, the wafers have similar defects to each other.
    Type: Application
    Filed: December 31, 2003
    Publication date: December 13, 2007
    Inventors: Richard Burch, Paul Lin, Spencer Graves, Eric Antonissen
  • Patent number: 7024642
    Abstract: A characterization vehicle includes a substrate having at least one layer (300), and a plurality of pairs of nested serpentine lines on a single surface of a single layer of the substrate (301a . . . 301h, 302a . . . 302h), each pair of nested serpentine lines having a shared pad between them (312a . . . 312h).
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: April 4, 2006
    Assignee: PDF Solutions, Inc.
    Inventors: Christopher Hess, David Stashower, Brian E. Stine, Larg H. Weiland, Richard Burch, Dennis J. Ciplickas
  • Publication number: 20040094762
    Abstract: A characterization vehicle includes a substrate having at least one layer (300), and a plurality of pairs of nested serpentine lines on a single surface of a single layer of the substrate (301a. . . 301h, 302a. . . 302h), each pair of nested serpentine lines having a shared pad between them (312a. . . 312h).
    Type: Application
    Filed: September 12, 2003
    Publication date: May 20, 2004
    Inventors: Christopher Hess, David Stashower, Brian E. Stine, Larg H. Weiland, Richard Burch, Dennis J. Ciplickas
  • Patent number: 6608840
    Abstract: The range of digital data communication services, such as a basic rate 2B1Q ISDN channel, to customer premises located beyond the industry standard achievable range of a two-wire loop can be extended by increasing the capacity of the ISDN line code from two information bits per symbol to three information bits per symbol, so as to reduce the effective symbol rate, which is error correction encoded to an effective 4B1H line code for defining a sixteen level PAM signal waveform, and employing enhanced low signal-to-noise ratio signal processing techniques in both the transmitter and receiver to accommodate the increased insertion loss of the two-wire line resulting from its extended length. Such enhanced low signal-to-noise ratio signal processing techniques include a Tomlinson precoder in the transmitter, and an adaptive linear equalizer and a module unit in the receiver.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: August 19, 2003
    Assignee: Adtran Inc.
    Inventors: Michael D. Turner, Kevin W. Schneider, Richard A. Burch, Richard L. Goodson
  • Publication number: 20020118702
    Abstract: The range of digital data communication services, such as a basic rate 2B1Q ISDN channel, to customer premises located beyond the industry standard achievable range of a two-wire loop can be extended by increasing the capacity of the ISDN line code from two information bits per symbol to three information bits per symbol, so as to reduce the effective symbol rate, which is error correction encoded to an effective 4B1H line code for defining a sixteen level PAM signal waveform, and employing enhanced low signal-to-noise ratio signal processing techniques in both the transmitter and receiver to accommodate the increased insertion loss of the two-wire line resulting from its extended length. Such enhanced low signal-to-noise ratio signal processing techniques include a Tomlinson precoder in the transmitter, and an adaptive linear equalizer and a module unit in the receiver.
    Type: Application
    Filed: April 24, 2002
    Publication date: August 29, 2002
    Applicant: Adtran, Inc.
    Inventors: Michael D. Turner, Kevin W. Schneider, Richard A. Burch, Richard L. Goodson
  • Patent number: 6393029
    Abstract: The range of digital data communication services, such as a basic rate 2B1Q ISDN channel, to customer premises located beyond the industry standard achievable range of a two-wire loop can be extended by increasing the capacity of the ISDN line code from two information bits per symbol to three information bits per symbol, so as to reduce the effective symbol rate, which is error correction encoded to an effective 4B1H line code for defining a sixteen level PAM signal waveform, and employing enhanced low signal-to-noise ratio signal processing techniques in both the transmitter and receiver to accommodate the increased insertion loss of the two-wire line resulting from its extended length. Such enhanced low signal-to-noise ratio signal processing techniques include a Tomlinson precoder in the transmitter, and an adaptive linear equalizer and a module unit in the receiver.
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: May 21, 2002
    Assignee: Adtran, Inc.
    Inventors: Michael D. Turner, Kevin W. Schneider, Richard A. Burch, Richard L. Goodson
  • Patent number: 6108354
    Abstract: A device system and method of detecting impairments in a communication network, involving: receiving during a plurality of time intervals equalized training signals which are produced from training symbols that have been transmitted over the network and equalized; generating reference symbols corresponding to the training symbols and equalized training signals; indexing the equalized training signals by their time intervals and corresponding reference symbols; calculating errors due to impairments from the indexed, equalized training signals; and detecting impairments in the network from the calculated impairment errors.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: August 22, 2000
    Assignee: Motorola Inc.
    Inventors: Christopher J. T. Scull, Richard A. Burch
  • Patent number: 6041483
    Abstract: A funerary urn comprises a top, a bottom and side walls connecting the side and bottom. The urn has an open area within a first storage space, the opening having a volume of between 0.25 and 2.5 cubic feet being defined by the top, bottom and side walls. The top, bottom and side walls have openings therein which allow passage of water into the storage space and allow air to pass out of the storage space. The urn, when it contains the ashes of a cremated animal and then immersed in water will attain a specific gravity of greater than 1.0 within three minutes. At least 80% by weight of the top, bottom and side walls consist essentially of materials which would decompose, degrade, dissolve or disperse in water so that the urn will lose its structural integrity within twelve months of continued immersion in water at 20.degree. C.
    Type: Grant
    Filed: May 15, 1997
    Date of Patent: March 28, 2000
    Assignee: Design Cast Studios LLC
    Inventor: Richard A. Burch
  • Patent number: 5999542
    Abstract: The range of digital data communication services, such as a basic rate 2B1Q ISDN channel, to customer premises located beyond the industry standard achievable range of a two-wire loop can be extended by increasing the capacity of the ISDN line code from two information bits per symbol to three information bits per symbol, so as to reduce the effective symbol rate, which is error correction encoded to an effective 4B1H line code for defining a sixteen level PAM signal waveform, and employing enhanced low signal-to-noise ratio signal processing techniques in both the transmitter and receiver to accommodate the increased insertion loss of the two-wire line resulting from its extended length. Such enhanced low signal-to-noise ratio signal processing techniques include a Tomlinson precoder in the transmitter, and an adaptive linear equalizer and a module unit in the receiver.
    Type: Grant
    Filed: August 12, 1998
    Date of Patent: December 7, 1999
    Assignee: Adtran, Inc.
    Inventors: Michael D. Turner, Kevin W. Schneider, Richard A. Burch, Richard L. Goodson