Patents by Inventor Richard C. Beaven

Richard C. Beaven has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4982402
    Abstract: In a multiprocessor system, an error occurring in any one of the CPUs may have an impact upon the operation of the remaining CPUs, and therefore these errors must be handled quickly. The errors are grouped into two categories: synchronous errors (those that must be corrected immediately to allow continued processing of the current instruction); and asynchronous errors (those errors that do not affect execution of the current instruction and may be handled upon completing execution of the current instruction). Since synchronous errors prevent continued execution of the current instruction, it is preferable that the last stable state conditions of the faulting CPU be restored and the faulting instruction reexecuted. These stable state conditions advantageously occur between the execution of each instruction. However, in a pipelined computer system, it is difficult to identify the beginning and ending of a selected instruction since multiple instructions are in process at the same time.
    Type: Grant
    Filed: February 3, 1989
    Date of Patent: January 1, 1991
    Assignee: Digital Equipment Corporation
    Inventors: Richard C. Beaven, Michael B. Evans, Tryggve Fossum, Ricky C. Hetherington, William R. Grundmann, John E. Murray, Ronald M. Salett