Abstract: An oscillator having a circuit for fine tuning the frequency thereof while minimizing any effect on the output amplitude thereof. A state variable oscillator employs an inverter amplifier having a negative feedback resistor R.sub.f, a first integrator, and a second integrator. 180.degree. feedback from the second integrator is fed back through resistors R.sub.i and R.sub.v to an inverting input of the inverter amplifier. 90.degree. feedback from the first integrator is fed back partially through resistors R.sub.n and R.sub.v and partially through resistor R.sub.m to the inverting input, and also through resistor R.sub.c to the non-inverting input. A field effect transistor provides a common return to the non-inverting input to control oscillator amplitude. If R.sub.i R.sub.m =R.sub.n R.sub.f then R.sub.v may be adjusted to vary the frequency of the oscillator output signal without affecting its amplitude.

Abstract: A method and circuit for quickly adjusting the frequency of a phase lock loop controlled oscillator to match a reference frequency signal by starting the reference frequency signal at essentially zero initial phase coincident with a zero crossing of the oscillator output. The reference frequency signal is provided by dividing a higher source frequency signal a predetermined amount. Upon receipt of an initialization signal the divider and the phase lock loop are inhibited. Upon the occurrance of a zero crossing the divider and loop are enabled so that the reference signal starts at zero phase within a predetermined period following the zero crossing, and the loop thereafter adjusts the oscillator frequency.

Abstract: A circuit for use in association with a sample and hold circuit for preventing a sampled signal voltage from changing with time. The storage capacitor port at the sample and hold circuit is connected through a resistor to a variable voltage divider so that by adjusting the tap of the divider the current through the resistor can be adjusted to match the bias current generated at the capacitor port by the sample and hold circuit. A temperature sensitive device is included in the voltage divider for varying tap voltage and, hence, the matching current with ambient temperature to compensate for corresponding changes in bias current. The voltage divider is connected between the sample and hold output and a common return path to ensure that the voltage at the tap is a function of the sampled voltage and the temperature only.

Abstract: An intermodulation test analyzer which automatically determines whether an SMPTE or CCIF intermodulation test is being conducted and switches its output accordingly is disclosed. This is accomplished by sensing the low frequency energy content of the test signal. This energy content is compared to a reference level representative of the low frequency energy content of a typical SMPTE test signal. Therefore, if the low frequency energy content of the input signal is greater than the reference level, the signal is treated as the SMPTE test signal. However, if the low frequency energy content is less than the reference level, the signal is processed as a CCIF test signal.

Abstract: A noise reducing circuit for a frequency discriminator is disclosed for providing a frequency discriminator with reduced sensitivity to noise. Reducing the sensitivity to noise allows certain distortion measurements, such as the well-known SINAD test for broadcast receivers, to be made in the presence of high noise levels.