Abstract: For identifying a preamble or other pattern in a binary bit stream, containing data coded to have a different average number of ones to zeroes from the pattern in question, a pattern detection circuit includes a shift register, a unitary adder and a comparison circuit. The shift register has a sufficient length that there is at least a high probability that the number of ones stored therein is different for the pattern in question from the range of number of ones found in that length of the data stream. The unitary adder counts the number of ones in the register, and this value is compared with the range of values which that length of the pattern should contain. If the pattern to be detected is a preamble used for bit synchronization, and the data are coded in a way which may lead to possibility of synchronization to a subharmonic, a ones-average detector may be used to disable the synchronization circuit for a local clock until the preamble is detected.

Abstract: A clock recovery and data separator system of the type described in U.S. Pat. No. 4,456,890 is improved by the inclusion of a detector for detecting the trend of instantaneous media speed variation (ISV). The system includes a phase locked loop in which the ISV trend detector is placed between the output of the phase detector and the input of an up/down counter whose output is passed through a digital to analog converter to control the VCO. The ISV trend detector provides a signal which partially compensates phase shift, thereby permitting rapid data recovery performance.

Abstract: A clock recovery system including a VCO responsive to a voltage signal for generating a clock signal. A phase detector includes a register and a PROM, the register counting the clock signal to derive the output clock signal. The PROM is responsive to input data and the count in the register to detect and store information concerning relative phase relationships. A counter contains a count from which the control voltage for the VCO is derived. The PROM is operable to alter the count in the counter, thereby performing frequency adjustments, and to alter the count in the register to perform phase adjustments. Also, a converter, operable by the phase detector, may also derive a voltage signal for damping purposes.