Abstract: A circuit is provided wherein the electronic properties of the circuit are varied by a magnetic actuator. The circuit includes a fixed substrate and a movable substrate. The magnetic actuator comprises a magnetic driver on an upper surface of the fixed substrate that is substantially overlapped by an HTS reaction plate on the lower surface of the fixed substrate. A tuning current applied through a continuous strip of HTS material in the magnetic driver induces a repulsive magnetic force causing the movable substrate to move with respect to the fixed substrate.

Abstract: Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor are described.

Abstract: The invention relates to methods and devices for precise geolocation of low-power, broadband, amplitude-modulated rf and microwave signals having poor coherency. The invention provides a basis for dramatic improvements in RF receiver technology, offering much higher sensitivity, very strong rejection of unintended signals, and novel direction finding techniques. When mounted on an airborne surveillance platform, the invention can detect and geolocate weak, broadband, incoherent RF and/or microwave signals. Embodiments of the invention are implemented by dual channel receivers (heterodyne or tuned-RF) that use crystal detection and Fast Fourier Transform (FFT) analysis for geolocation. Geolocation is accomplished using a subsystem of phased arrays and an angle of arrival technique.

Abstract: Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor are described.

Abstract: An IC laser array package is provided wherein standard CMOS integrated circuit (IC) processes are used for fabricating the controller for the laser array and wherein p-channel MOSFET devices are used as switches with the controller which short the anode of the selected laser in the array (connected to the drain of the p-channel MOSFET switches) to ground. In this structure, the modulating signal from the driver input can be applied to the common cathode substrate of the laser array bar in a standard package, along with a negative dc bias current provided from the negative voltage dc bias package pin through an inductor, in the same built-in bias tee manner previously used with a standard single-laser 14-pin package. Because the p-channel MOSFETs are used only as switches, their ft values are typically not a material hindrance to the circuit operation.

Abstract: Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor are described. One exemplary aspect provides a power semiconductor device including a semiconductive substrate having a surface; and a power transistor having a planar configuration and comprising a plurality of electrically coupled sources and a plurality of electrically coupled drains formed using the semiconductive substrate and adjacent the surface.

Abstract: Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor are described.

Abstract: Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor are described.

Abstract: A tunable filter having a fixed substrate, a first and second plate comprising a high-temperature superconductor material on the fixed substrate, a movable substrate, a mechanical driver attached to the fixed substrate and the movable substrate, a floating plate comprising a high-temperature superconductor material on the fixed substrate wherein the floating plate, the first plate, and the second plate define a gap, and wherein the gap is varied by length changes in the mechanical driver is provided.

Abstract: A synthetic diamond wafer grown by deposition from a plasma has a smooth, substrate side face and a rough, deposition side face. The rough face is coated with a bonding agent which fills the valleys and is finished so that its surface is parallel to the substrate side face to permit photolithographic processing of the wafer. Also disclosed is a multi-wafer laminate of two or more diamond film layers bonded together with an interlayer. Smooth, flat outer faces of the layers are oriented mutually parallel. The inner, bonded faces may be rough. A filler of diamond particles in the bonding agent improves the thermal conductivity of the laminate.

Abstract: The disclosure is directed to an improved circuit and method which utilizes a plurality of generally planar diamond substrate layers. Electronic circuit elements are mounted on each of the substrate layers, and the substrate layers are disposed in a stack. Heat exchange means can be coupled generally at the edges of the substrate layers. In a disclosed embodiment, a multiplicity of generally planar diamond substrate layers and a multiplicity of generally planar spacer boards are provided. Each of the substrate layers has mounted thereon a multiplicity of electronic elements and conductive means for coupling between electronic elements. In general, at least some of the electronic elements on the substrate layers comprise integrated circuit chips. The substrate layers and spacer boards are stacked in alternating fashion so that spacer boards are interleaved between adjacent substrate layers.

Abstract: A synthetic diamond wafer grown by deposition from a plasma has a smooth, substrate side face and a rough, deposition side face. The rough face is coated with a bonding agent which fills the valleys and is finished so that its surface is parallel to the substrate side face to permit photolithographic processing of the wafer. Also disclosed is a multi-wafer laminate of two or more diamond film layers bonded together with an interlayer. Smooth, flat outer faces of the layers are oriented mutually parallel. The inner, bonded faces may be rough. A filler of diamond particles in the bonding agent improves the thermal conductivity of the laminate.

Abstract: A V.sub.BB input threshold potential with feedback circuitry is used to stabilize all of the logic inputs on an GaAs IC to ECL compatible levels over a normal temperature range and normal power supply variations. The system called "V.sub.BB -Feedback" uses "zero translation delay" direct Capacitor Diode Fet Logic (CDFL) inputs. This is an extension of the CDFL circuit approach in which the voltage across the input level shift circuitry on all inputs is adjusted to maintain a threshold voltage equal to the dc potential on an "extra" V.sub.BB input in spite of variations of temperature, power supply voltages or processing parameters such as MESFET pinchoff voltage. A dc potential (V.sub.BB) is applied to the "extra" V.sub.BB input, which is an additional input that is essentially identical to the actual logic inputs. All of the logic input threshold voltages are then slaved to the V.sub.BB dc potential applied to the "extra" V.sub.BB input.

Abstract: A data communication system for general purposes having a new ternary carrier frequency shift keying (TCSK) signal. The system is applied to a utility load control by transmission of a sub-carrier of an FM broadcast channel. It is decoded by a receiver, SCA decoder, TCSK filter and a two level or binary converter and used to communicate to a pre-programmed microprocessor which enables various load control functions to be performed. The general system also is given for a QPSK (quadraphase shift keying) operating system.A data transmission filter is split between the transmitter and receiver and is operated in cascade to give individual interference filtering at each end of the transmission while also providing combined action and wave shaping. A high accuracy FM decoder using zero crossing detection enables data recovery with simple circuits. A novel random time load restoration circuit for ramp-up is disclosed. A fail safe relay operator is also disclosed.

Abstract: A random access memory circuit for use with positive and negative supply voltages, a read enable line, an output line, and write "1" and "0" lines includes first, second, third, and fourth level shifting diodes. A first input isolation diode is connected between the write "1" line and the first level shifting diode. A second input isolation diode is connected between the write "0" line and the cathode of the third level shifting diode. The drain of a first write FET is connected to the anode of the third diode, the source is connected to the read enable line, and the gate is connected to the cathode of the second level shifting diode. A second write FET has its drain connected to the anode of the first level shifting diode, its source connected to the read enable line, and its gate connected to the cathode of the fourth diode. An output buffer FET is connected by its source to the read enable line, by its gate to the cathode of the fourth diode.

Abstract: Disclosed is a logic circuit with a plurality of AND logic elements, each including a plurality of Schottky diodes with each cathode connected to a logic input and the anodes connected in common to establish an AND output. A diode pull up FET is provided for each AND output, with the source connected to the AND output, the gate connected to the source, and the drain connected to a source of positive bias potential. An OR logic element includes a plurality of Schottky diodes with each anode connected to one of the AND outputs and the cathodes connected in common to establish an OR output, while a diode pull down FET has its drain connected to the OR output, with the gate connected to the source and the source connected to a source of negative bias potential. A level shifting diode is placed between the OR output and the pull down FET. An output FET is connected through its gate to the drain of the diode pull down FET, with the source connected to ground and the drain providing a logic output from the circuit.

Abstract: A logic circuit is provided which uses Schottky barrier switching diodes to perform the "OR" logic function on logic inputs. The outputs from the switching diodes control the gate of a field-effect transistor (FET) which provides logic inversion and gain. The source of the FET is grounded and its drain provides the output of the logic circuit. Bias current for the switching diodes and gate turn-off current for the FET are provided by a pull down, and a pull up is provided to operate the FET. In a second embodiment, two separate groups of switching diodes control separate gates of a dual-gated FET to provide a two-level "OR/NAND" logic circuit. In a third embodiment, the outputs from a pair of two-level logic circuits are joined to provide a three-level "OR/NAND/WIRED-AND" logic circuit.

Abstract: A charge coupled device has a semi-insulating semiconductor for a substrate. Resistivity of the semiconductor is at least 10.sup.6 ohm cm. A semi-conductive layer is grown epitaxially or is implanted on the substrate to form a thin, active, charge transport layer. A row of parallel, closely spaced gates on the charge transport layer provides individual storage wells in the charge transport layer. In a preferred embodiment, ohmic contacts adjacent the first and last gates in the row of gates provide a means for injecting a signal into the charge transport layer and a means for detecting the signal. Preferably, the substrate is semi-insulating GaAs and the gates are Schottky barrier gates.

Abstract: A narrow-band, inverted homo-heterojunction avalanche photodiode, configured in the shape of a mesa situated upon a substrate which is transparent to selected light energy wavelengths. The diode is inverted for operation such that the incoming light energy enters the substrate side, passes through a wavelength selective buffer layer and is absorbed upon entering the succeeding, active region. Avalanche gain is attained by drift from the area of absorption to the high field p-n homo-heterojunction located immediately thereafter. The device exhibits low levels of noise during operation because absorption is occurring in a low field region and because the ionization and breakdown noise associated with lattice mismatches is avoided through the formation of the p-n homo-heterojunction in one continuous growth process. Appropriate passivation of the mesa walls inhibits surface leakage and breakdown effects.

Abstract: A narrow-band, inverted homo-heterojunction avalanche photodiode, configured in the shape of a mesa situated upon a substrate which is transparent to selected light energy wavelengths. The diode is inverted for operation such that the incoming light energy enters the substrate side, passes through a wavelength selective buffer layer and is absorbed upon entering the succeeding, active region. Avalanche gain is attained by drift from the area of absorption to the high field p-n homo-heterojunction located immediately thereafter. The device exhibits low levels of noise during operation because absorption is occurring in a low field region and because the ionization and breakdown noise associated with lattice mismatches is avoided through the formation of the p-n homo-heterojunction in one continuous growth process. Appropriate passivation of the mesa walls inhibits surface leakage and breakdown effects.