Abstract: A semiconductor structure having at least three types of wells which may be of different doping levels and methods of manufacturing such a structure, are disclosed. In one method, regions which will become active devices are protected with a nitride layer as the associated well-regions are implanted. In another method, previously implanted wells are covered with thick oxide which in combination with the nitride layer provides automatic alignment of adjacent wells. In yet another method, implanted wells are covered with oxide while a last well is implanted with this last well being defined by both thick oxide and photoresist. All methods avoid a masking step and avoid the need for aligning the edge of a later photoresist mask with the edge of an earlier photoresist mask. The structures formed by these methods may have heavily-doped P wells, heavily-doped N wells, and lightly-doped P or N wells, or both, for forming higher breakdown voltage devices on the same chip with lower breakdown voltage devices.

Abstract: An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends through the recessed dielectric portion and extends further into the monocrystalline silicon body than the recessed portion. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body.

Abstract: An integrated circuit structure having substrate contacts formed as a part of the isolation structure and method for making the same is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends from the side of the recessed dielectric portion opposite to that portion at the surface of said body into the monocrystalline silicon body. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation.

Abstract: An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends through the recessed dielectric portion and extends further into the monocrystalline silicon body than the recessed portion. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body.

Abstract: An improved field effect transistor device in a monocrystalline semiconductor body provided with source and drain regions and a gate electrode disposed over the channel between the source and drain regions wherein at least the drain region is formed of a first region where the impurity concentration increases with depth with the peak concentration being spaced inwardly from the major surface, and a second region located within the first region having a peak impurity concentration at the major surface. The drain region structure in operation promotes the current flow between the source and drain to flow deeper in the channel region and spaced from the gate dielectric layer.In the method for forming the field effect transistor, an impurity is introduced into the semiconductor body underlying at least the ultimate drain region, an epitaxial semiconductor layer deposited, and a second impurity region formed over the first region to form the drain contact.

Abstract: An improved field effect transistor device in a monocrystalline semiconductor body provided with source and drain regions and a gate electrode disposed over the channel between the source and drain regions wherein at least the drain region is formed of a first region where the impurity concentration increases with depth with the peak concentration being spaced inwardly from the major surface, and a second region located within the first region having a peak impurity concentration at the major surface. The drain region structure in operation promotes the current flow between the source and drain to flow deeper in the channel region and spaced from the gate dielectric layer.In the method for forming the field effect transistor, an impurity is introduced into the semiconductor body underlying at least the ultimate drain region, an epitaxial semiconductor layer deposited, and a second impurity region formed over the first region to form the drain contact.

Abstract: The device structure is a bi-polar transistor having a region of inert atoms located in the collector adjacent to the base-collector junction. Another embodiment of the invention is a complementary insulated gate field effect transistor (IGFET) structure having N and P channel IGFETs with regions of implanted ions beneath the source and drain of one or both transistors, and/or annular regions projecting inwardly from the surface that surround or separate the different types of IGFETs.

Abstract: An improved field effect transistor device in a monocrystalline semiconductor body provided with source and drain regions and a gate electrode disposed over the channel between the source and drain regions wherein at least the drain region is formed of a first region where the impurity concentration increases with depth with the peak concentration being spaced inwardly from the major surface, and a second region located within the first region having a peak impurity concentration at the major surface. The drain region structure in operation promotes the current flow between the source and drain to flow deeper in the channel region and spaced from the gate dielectric layer.In the method for forming the field effect transistor, an impurity is introduced into the semiconductor body underlying at least the ultimate drain region, an epitaxial semiconductor layer deposited, and a second impurity region formed over the first region to form the drain contact.