Abstract: A computer is used to estimate a fabrication yield for a semiconductor product under design which includes a plurality of integrated circuit dies, each of which includes a memory cache having a predetermined redundancy scheme in the form of redundant rows and/or columns. A bitmap failure analysis of an existing semiconductor product including a plurality of integrated circuit dies having bitmap failure modes that are comparable to those of the product being designed is performed to obtain a number of failed caches. An observed repair rate is computed as a ratio of a number of the failed caches that can be repaired by the predetermined redundancy scheme to the number of failed caches. A model repair rate for the predetermined redundancy scheme which approximates the observed repair rate is computed using a multiple Poisson model including computed average numbers .lambda. of failures for the failure modes respectively. The numbers .lambda.

Abstract: An improved method is provided for defining interconnect patterns in an integrated circuit fabricated on a semiconductor wafer. The improvement comprises the step of immersing the wafer in a weak base solution, prior to etching a titanium-tungsten barrier layer, so as to remove from the wafer chlorides and flourides remaining as a result of a previous step of etching a conductor layer. In a preferred embodiment of the invention, a step of immersing the wafer in a strong acid solution is also performed to remove chlorides from the wafer.