Abstract: A memory refresh control scheme is provided wherein the refresh timing and address signals are independent of memory configuration or the configuration of an interface unit. Since the system relates to a distributed memory arrangement, the refresh control signal and the refresh address signals are simultaneously sent to the corresponding address portions of each of the concerned memory sections and to the interface units. The logic involved in generating the refresh signal includes a first counter, driven by the system clock, which periodically generates the refresh request control signal. A second counter generates a digital address for the portion of the memory units to be refreshed. The second counter is incremented by each successive output control signal from the first counter.

Abstract: In a computer system, there is included a memory unit which includes a volatile memory store, and a memory control circuit connected with the memory unit thereby permitting the computer system to be operated in a step mode, the memory control circuit comprising a step clock generator which generates a gated clock signal. A register element receives a step command signal, an indication from the computer system that the memory unit is to be operated in the step mode, and generates the step mode control signal in response to said step command signal. A shift register receives a strobe command signal from the computer system indicating a request for a memory cycle, and delays the strobe command signal, each stage of the shift register representing a successive step when the computer system is operated in the step mode.