Patents by Inventor Richard C. Saito

Richard C. Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Algorithm and methodology for the polygonalization of sparse circuit schematics
    Patent number: 6904571
    Abstract: An method of creating a physical layout of an integrated circuit. A schematic file (600) is mapped directly to a physical layout using the location of elements and routing of interconnections as specified in the schematic file (600). The method takes advantage of constraints on the schematic design to provide the layout file (675) quickly, without complex routing programs. Design rules violations are anticipated and corrected in some cases. In other cases, the design rule violations are annotated, if the designer intentionally placed them in the design.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: June 7, 2005
    Assignee: Altera Corporation
    Inventors: Dominik J. Schmidt, Perry Chun, Richard C. Saito, Eugene Y. Chen
  • Algorithm and methodology for the polygonalization of sparse circuit schematics
    Patent number: 6480995
    Abstract: An method of creating a physical layout of an integrated circuit. A schematic file (600) is mapped directly to a physical layout using the location of elements and routing of interconnections as specified in the schematic file (600). The method takes advantage of constraints on the schematic design to provide the layout file (675) quickly, without complex routing programs. Design rules violations are anticipated and corrected in some cases. In other cases, the design rule violations are annotated, if the designer intentionally placed them in the design.
    Type: Grant
    Filed: April 14, 1997
    Date of Patent: November 12, 2002
    Assignee: Altera Corporation
    Inventors: Dominik J. Schmidt, Perry Chun, Richard C. Saito, Y. Eugene Chen
  • Apparatus and method for automatically generating circuit layouts
    Patent number: 6321367
    Abstract: A method of automatically generating a custom device layout includes the step of specifying a device type and an associated set of device parameters. The device type is then matched to a selected cell in a cell library. Physical layout regions of the selected cell are then selectively modified in accordance with the device parameters. The physical layout regions may also be selectively modified in accordance with technology design rules in a design rule library. The physical layout regions of the selected cell are then drawn.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: November 20, 2001
    Assignee: Altera Corporation
    Inventors: Perry Chun, Richard C. Saito, Y. Eugene Chen