Abstract: A method of planarizing an electrically insulative layer formed over a non-planar integrated circuit substrate having raised portions. After the electrically insulative layers are deposited over such substrate, the layer has elevations corresponding to the underlying raised portions of the substrate. A masking layer is formed on the electrically insulative layer having at least one opening therethrough coincident with an elevation in the insulative layer; this opening has smaller lateral dimensions than the coincident elevation, thereby facilitating alignment. The elevation in the insulative layer exposed in said at least one opening is then etched to the level of the unelevated portion of the layer, and the insulative layer is then resputtered for a period of time sufficient to planarize the remainder of such etched elevation to the level of the unelevated portions.