Abstract: Presently provided are inhibitors of TD02 and IDO1 and pharmaceutical compositions thereof, useful for modulating an activity of tryptophan 2,3 dioxygenase and indoleamine 2,3-dioxygenase 1; treating immunosuppression; treating a medical conditions that benefit from the inhibition of tryptophan degradation; enhancing the effectiveness of an anti-cancer treatment comprising administering an anti-cancer agent; and treating tumor-specific immunosuppression associated with cancer.

Abstract: Provided are various embodiments relating to anti-IL4R antibodies that bind to canine IL4R. In various embodiments, such anti-IL4R antibodies can be used in methods to treat IL4/IL13-induced conditions, such as atopic dermatitis, allergic dermatitis, pruritus, asthma, psoriasis, scleroderma and eczema, in companion animals, such as canines and felines. Also provided are various embodiments relating to variant IgG Fc polypeptides and variant light chain constant regions of companion animal species for the preparation of antibodies or bispecific antibodies.

Abstract: Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.

Abstract: Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.

Abstract: A device is described in one embodiment that includes a micro-electro-mechanical systems (MEMS) device disposed on a first substrate and a semiconductor device disposed on a second substrate. A bond electrically connects the MEMS device and the semiconductor device. The bond includes an interface between a first bonding layer including silicon on the first substrate and a second bonding layer including aluminum on the second substrate. The physical interface between the aluminum and silicon (e.g., amorphous silicon) can provide an electrical connection.

Abstract: The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum.

Abstract: Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum -based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.

Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.

Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a method for forming a via structure includes forming a via in a semiconductor substrate, wherein via sidewalls of the via are defined by the semiconductor substrate; forming a dielectric layer on the via sidewalls; removing the dielectric layer from a portion of the via sidewalls; and forming a conductive layer to fill the via, wherein the conductive layer is disposed over the dielectric layer and the portion of the via sidewalls. In an example, the dielectric layer is an oxide layer.

Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a method for forming a via structure includes forming a via in a semiconductor substrate, wherein via sidewalls of the via are defined by the semiconductor substrate; forming a dielectric layer on the via sidewalls; removing the dielectric layer from a portion of the via sidewalls; and forming a conductive layer to fill the via, wherein the conductive layer is disposed over the dielectric layer and the portion of the via sidewalls. In an example, the dielectric layer is an oxide layer.

Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.

Abstract: A semiconductor device includes a substrate wafer, a dielectric layer overlying the substrate wafer, a patterned conductor layer in the dielectric layer, and a first barrier layer overlying the conductor layer. A silicon top wafer is bonded to the dielectric layer. A via is formed through the top wafer and a portion of the dielectric layer to the first barrier layer. A sidewall dielectric layer is formed along inner walls of the via, adjacent the top wafer to a distance below an upper surface of the top wafer, forming a sidewall dielectric layer shoulder. A sidewall barrier layer is formed inward of the sidewall dielectric layer, lining the via from the first barrier layer to the upper surface of the top wafer. A conductive layer fills the via and a top barrier layer is formed on the conductive layer, the sidewall barrier layer, and the top wafer.

Abstract: A semiconductor device includes a substrate wafer, a dielectric layer overlying the substrate wafer, a patterned conductor layer in the dielectric layer, and a first barrier layer overlying the conductor layer. A silicon top wafer is bonded to the dielectric layer. A via is formed through the top wafer and a portion of the dielectric layer to the first barrier layer. A sidewall dielectric layer is formed along inner walls of the via, adjacent the top wafer to a distance below an upper surface of the top wafer, forming a sidewall dielectric layer shoulder. A sidewall barrier layer is formed inward of the sidewall dielectric layer, lining the via from the first barrier layer to the upper surface of the top wafer. A conductive layer fills the via and a top barrier layer is formed on the conductive layer, the sidewall barrier layer, and the top wafer.

Abstract: Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.

Abstract: The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum.

Abstract: An apparatus is provided for facilitating cooling of an electronics rack employing an air delivery structure coupled to the electronics rack. The air delivery structure delivers air flow at a location external to the electronics rack and in a direction to facilitate mixing thereof with re-circulating exhausted inlet-to-outlet air flow from the air outlet side of the electronics rack to the air inlet side thereof. The delivered air flow is cooler than the re-circulating exhausted inlet-to-outlet air flow and when mixed with the re-circulating air flow facilitates lowering air inlet temperature at a portion of the air inlet side of the electronics rack, thereby enhancing cooling of the electronics rack.

Abstract: An isolation valve assembly, a coolant connect/disconnect assembly, a cooled multi-blade electronics center, and methods of fabrication thereof are provided employing an isolation valve and actuation mechanism. The isolation valve is disposed within at least one of a coolant supply or return line providing liquid coolant to the electronics subsystem. The actuation member is coupled to the isolation valve to automatically translate a linear motion, resulting from insertion of the electronics subsystem into the operational position within the electronics housing, into a rotational motion to open the isolation valve and allow coolant to pass. The actuation mechanism, which operates to automatically close the isolation valve when the liquid cooled electronics subsystem is withdrawn from the operational position, can be employed in combination with a compression valve coupling, with one fitting of the compression valve coupling being disposed serially in fluid communication with the isolation valve.

Abstract: A cooling apparatus and a direct cooling impingement module are provided, along with a method of fabrication thereof. The cooling apparatus and direct impingement cooling module include a manifold structure and a jet orifice plate for injecting coolant onto a surface to be cooled. The jet orifice plate, which includes a plurality of jet orifices for directing coolant at the surface to be cooled, is a unitary plate configured with a plurality of jet orifice structures. Each jet orifice structure projects from a lower surface of the jet orifice plate towards the surface to be cooled, and includes a respective jet orifice. The jet orifice structures are spaced to define coolant effluent removal regions therebetween which facilitate removal of coolant effluent from over a center region of the electronic component being cooled to a peripheral region thereof, thereby reducing pressure drop across the jet orifice plate.

Abstract: Cooling apparatuses and methods are provided for cooling an assembly including a substrate supporting multiple electronics components. The cooling apparatus includes: multiple discrete cold plates, each having a coolant inlet, a coolant outlet and at least one coolant chamber disposed therebetween; and multiple coolant-carrying tubes, each tube extending from a respective cold plate and being in fluid communication with the coolant inlet or outlet of the cold plate. An enclosure is provided having a perimeter region which engages the substrate to form a cavity with the electronics components and cold plates being disposed within the cavity. The enclosure is configured with multiple bores, each bore being sized and located to receive a respective coolant-carrying tube of the tubes extending from the cold plates. Further, the enclosure is configured with a manifold in fluid communication with the tubes for distributing coolant in parallel to the cold plates.

Abstract: Cooling apparatuses and methods are provided for cooling an assembly including a planar support structure supporting multiple electronics components. The cooling apparatus includes: multiple discrete cold plates, each having a coolant inlet, coolant outlet and at least one coolant carrying channel disposed therebetween; and a manifold for distributing coolant to and exhausting coolant from the cold plates. The cooling apparatus also includes multiple flexible hoses connecting the coolant inlets of the cold plates to the manifold, as well as the coolant outlets to the manifold, with each hose segment being disposed between a respective cold plate and the manifold. A biasing mechanism biases the cold plates away from the manifold and towards the electronics components, and at least one fastener secures the manifold to the support structure, compressing the biasing mechanism, and thereby forcing the parallel coupled cold plates towards their respective electronics components to ensure good thermal interface.