Abstract: A cooking barrier that is movable to minimize harm caused by splashes of food during the cooking and frying process. The cooking barrier includes a mesh or screen material movable between a storage condition and an operable condition preventing splattering food particles from penetrating the cooking barrier. The cooking barrier may include a plurality of mesh or screen materials oriented in vertical, horizontal and there between so as to define a cooking area for preventing the splattering food particles from escaping from.

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

Abstract: The present invention provides a method and system for routing a group of scan chains to a group of processor resources in a semiconductor chip. The group of processor resources is arranged in rows or columns. The group of processor resources in each row or column is connected through a plurality of scan chains. The first processor resource in each row or column is connected to input scan-chain pins, and the last processor resource in each row or column is connected to output scan-chain pins. A test-pattern generator, generating test signals, sends the test signals to the group of processor resources by using the group of scan chains within the semiconductor chip. The responses of the processor resources corresponding to the test signals are analyzed to detect and locate any error in the manufacture of the semiconductor chip.

Abstract: The present invention provides a method and system for routing a group of scan chains to a group of processor resources in a semiconductor chip. The group of processor resources is arranged in rows or columns. The group of processor resources in each row or column is connected through a plurality of scan chains. The first processor resource in each row or column is connected to input scan-chain pins, and the last processor resource in each row or column is connected to output scan-chain pins. A test-pattern generator, generating test signals, sends the test signals to the group of processor resources by using the group of scan chains within the semiconductor chip. The responses of the processor resources corresponding to the test signals are analyzed to detect and locate any error in the manufacture of the semiconductor chip.

Abstract: A thermal by-pass valve for fluids includes a sleeve having an inlet opening, and two outlet openings. One of the outlet openings functions as a by-pass opening. A bi-metallic metal coil is enclosed within the sleeve. The coil has one end securely attached to a cap, which cap incorporates an inlet for a fluid. The cap is attached to the inlet opening of the sleeve. The bi-metallic coil is designed to rotate the sleeve when the temperature of the fluid exceeds or drops below a designated threshold temperature.

Abstract: A thermal by-pass valve for fluids includes a sleeve having an inlet opening, and two outlet openings. One of the outlet openings functions as a by-pass opening. A bi-metallic metal coil is enclosed within the sleeve. The coil has one end securely attached to a cap, which cap incorporates an inlet for a fluid. The cap is attached to the inlet opening of the sleeve. The bi-metallic coil is designed to rotate the sleeve when the temperature of the fluid exceeds or drops below a designated threshold temperature.

Abstract: Apparatus for and method of enhancing the performance of multi-port internal cached DRAMs and the like by providing for communicating to system I/O resources messages sent by other such resources and the message location within the DRAM array, and further providing for efficient internal data bus usage in accommodating for both small and large units of data transfer.

Abstract: A novel networking architecture and technique for reducing system latency caused, at least in part, by access contention for usage of common bus and memory facilities, wherein a separate data processing and queue management forwarding engine and queue manager are provided for each I/O module to process packet/cell control information and delivers queuing along a separate path that eliminates contention with other resources and is separate from the transfer of packet/cell data into and from the memory.