Abstract: A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design.

Abstract: A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design.

Abstract: A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit design to verify compliance with a set of design rules; (b) generating a results database of design rule violations detected by the physical design validation; (c) identifying locations in the integrated circuit design from the results database for making design corrections according to a post-processing rule deck so that the locations of the design corrections comply with the set of design rules; and (d) implementing the design corrections in the integrated circuit design.

Abstract: A method of implementing an engineering change order includes steps of: (a) receiving as input an integrated circuit design; (b) receiving as input an engineering change order to the integrated circuit design; (c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; (d) performing a routing of the integrated circuit design that excludes routing of any net that is not enclosed by the window; (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and (f) generating as output the revised integrated circuit design.

Abstract: A method and computer program product for verifying an incremental change to an integrated circuit design include receiving as input an integrated circuit design database and an engineering change order. Objects in the integrated circuit design database are identified and marked to indicate a current state of the integrated circuit design database. The engineering change order is applied to the integrated circuit design database, and the integrated circuit design database is analyzed to generate a list of incremental changes to the integrated circuit design database resulting from the engineering change order. Objects in the integrated circuit design database included in the list of incremental changes are identified and marked to distinguish objects in the integrated circuit design database that were changed from the current state. The marked integrated circuit design database distinguishing the objects that were changed from the current state is generated as output.

Abstract: A method of partitioning an integrated circuit design for physical design verification includes steps of receiving as input a representation of an integrated circuit design having a number of physical design layers and a composite run deck specifying rule checks to be performed on the integrated circuit design. The composite run deck is partitioned into partitioned run decks so that the number of physical design layers referenced by each of the partitioned run decks is a minimum. The representation of the integrated circuit design is parsed to filter only the physical design layers required for each of the partitioned run decks into a filtered data deck for each of the partitioned run decks. The filtered data deck is generated as output for each of the partitioned run decks.

Abstract: A method of repeater insertion in a hierarchical integrated circuit includes defining an initial floorplan for a parent macro at a parent level in a hierarchical circuit design; passing outline and pin locations from the parent macro to a child macro sharing a common area with the parent macro; defining or modifying a floor plan for the child macro at a child level in the hierarchical circuit design in response to the outline and pin locations passed from the parent macro; passing physical restrictions in the child macro from the child macro to the parent macro; determining a location for a cell at the parent level of the hierarchical circuit design in an area of the parent macro shared by the child macro in response to the physical restrictions passed from the child macro; passing physical constraints in the parent macro associated with placement and routing of the cell from the parent level to the child macro; and generating an abstract representation for the child macro at the child level that includes an

Abstract: A method of repeater insertion in a hierarchical integrated circuit includes defining an initial floorplan for a parent macro at a parent level in a hierarchical circuit design; passing outline and pin locations from the parent macro to a child macro sharing a common area with the parent macro; defining or modifying a floor plan for the child macro at a child level in the hierarchical circuit design in response to the outline and pin locations passed from the parent macro; passing physical restrictions in the child macro from the child macro to the parent macro; determining a location for a cell at the parent level of the hierarchical circuit design in an area of the parent macro shared by the child macro in response to the physical restrictions passed from the child macro; passing physical constraints in the parent macro associated with placement and routing of the cell from the parent level to the child macro; and generating an abstract representation for the child macro at the child level that includes an

Abstract: A method determines the behavior of a logic cell that receives input signals resulting in a narrow pulse or "glitch." If the pulse width of the output pulse is narrower than a pulse rejection period, the output pulse is rejected and is not propagated to subsequent logic cells connected to the output. The method employs a first internal logic cell model which is assigned an inertial delay function, and a second internal logic cell model which is assigned a transport delay function. In combination, the first and second logic cell models result in an effective propagation delay value, subject to the pulse rejection feature. An exemplary VHDL model is disclosed. A program product embodies a logic cell model in VHDL providing pulse rejection capabilities for output pulses with pulse width smaller than a pulse rejection period.

Abstract: Format-independent electronic circuit descriptions are generated by providing incompatible sets of naming conventions, providing translation rules for generating circuit element names which satisfy all supported naming conventions, and modifying element names in accordance with the translation rules. Supported circuit descriptions may represent netlists defined by high-level design languages such as Verilog, EDIF, VHDL, and so forth, or may represent schematics or other symbolic representations. Any element associated with any input circuit representation may be tested or modified to ensure compatibility, such as the naming of logic cell types and instances, the naming of nets interconnecting logic cells, and the naming of input, output, and bidirectional ports. In a preferred embodiment, an element name to be resolved is inserted into a set of element names to determine whether the name is unique. If not, the proposed name is modified according to a set of modification rules until uniqueness is achieved.

Abstract: A method and apparatus for approximating power dissipation using a computer-assisted engineering (CAE) system. Initially, a determination is made of the capacitive load for each cell in a netlist for the CMOS circuit, preferably from cell library data sheets. In addition, the capacitive loads of the interconnects between stages are estimated. A switching rate for each cell is then calculated using one of two alternative methods. The first method assumes that the patterns of input signals are statistically independent, and thus estimates the switching rate from the structure of the cell and the switching rates of the inputs. The second method uses known information concerning the relative times when the input signals are high or low to determine the switching rate of the cell. Once the switching rate is known, the output frequency for the cell can be determined. The power dissipation for each cell is then calculated by multiplying the output frequency by the capacitive load.

Abstract: A method for approximating the delay time of an excitation through a logic cell using the summation of a base delay, which is a function of delay coefficients for the cell and the total output load capacitance of the cell, and a rise/fall time correction, which is determined from the output rise/fall time of the driving cell and the sensitivity of the analyzed cell to rise/fall time. Other corrections/compensating factors include a performance derating factor which accounts for the multiplicative effects of operating voltage, temperature and process.