Abstract: A parity SRAM having the capability to support byte parity is provided. The parity SRAM uses four (4) independent byte write enable (BWE.sub.x) signals to enable a write amplifier to individually write a single parity bit to a selected memory location. The SRAM is designed to function in either a parity or a non-parity mode. A bonding option pad is connected to parity control logic circuitry, and determines whether the SRAM will function in the parity mode or the non-parity mode. The parity control logic circuitry generates a parity signal, based on the electrical connection of the option pad. Thus, when the option pad is connected to ground, the parity option is selected, whereas, when the option pad is connected to a positive power supply, then non-parity functionality is selected. When parity functionality is selected, the the SRAM will allow the four (4) independent BWE.sub.x signals to individually enable the write amplifier.

Abstract: A CMOS DRAM has an array in a well which is pumped to a voltage greater than the power supply voltage. The transfer devices of the memory cells in the array are of a conductivity type opposite to that of the well. The transfer devices each have a source/drain of the opposite conductivity type to that of the well which is connected to a bit line. The bit line will tend to rise in voltage at power-up which has the potential of forward biasing the PN junction between the source/drain and the well. The bit line rise is due to a word-line rise the rate of which is controlled so that the bit line rise does not exceed the rise in array voltage. The bit lines are ensured of being separated in voltage at the beginning of the first active cycle by enabling the N channel portion of the sense amplifier during power-up. The P channel portion of the sense amplifier is disabled during power-up to avoid too rapid of a rise in voltage on the bit lines.

Abstract: A cache TAG, which has a compare mode, an and/or/invert mode, and a read mode, has a programmable comparator which receives an external data signal and an output from an array of memory cells and provides an output to a secondary amplifier. The secondary amplifier provides an output to a match comparator in the compare mode and the and/or/invert mode and to an output buffer in the read mode. The programmable comparator is programmable according to the mode of the cache TAG. The compartor uses selectively enabled transmission gates which provide minimal delay in providing the appropriate data to the secondary sense amplifiers.

Abstract: A read/write memory has bit line pairs variously having a first or a second true/complement orientation. Data is selectively coupled to and from the bit line pairs to and from a data line pair via a column decoder. The memory has redundant bit line pairs aligned in the first true/complement arrangement. When a redundant bit line pair is implemented, the logic state of the data is inverted both for reading and for writing if the replaced bit line pair is of the second true/complement orientation. This results in the voltage impressed onto the memory cell for a given logic state is the same for the redundant bit line pair as for the bit line pair that it replaced.

Abstract: A buffer circuit is provided for buffering an input clock signal having TTL voltage levels to provide an output clock signal having MOS voltage levels. A reference voltage portion provides an accurate bias voltage to a first node. A voltage translation portion is coupled between an input and the first node. An inverter portion has a first input connected to the first node, a second input for receiving the input clock signal, and an output for providing the output clock signal. A clamping portion is connected to the first node to minimize the bias voltage potential.

Abstract: A memory management unit of use in a memory management system. The memory management unit selectively maps a logical address to a respective physical address in accordance with a selected one of a plurality of segment descriptors, each of which defines a logical-to-physical address mapping and a range of address spaces for which such mapping is valid. The mapping is achieved using an improved associative memory circuit. Means are provided to detect mapping conflicts between new segment descriptors and segment descriptors already stored, and to prevent the storage of such conflicting segment descriptors. A method and circuit are provided to coordinate the parallel operation of a plurality of the memory management units or the like.

Abstract: A three state output circuit which pulls down the output node thereof to a first supply voltage in response to an assert signal, pulls up the output node to a second supply voltage in response to a rescind signal, and then presents a high impedance on the output node immediately after the output node is pulled up to a selected reference voltage.

Abstract: An MOS input buffer circuit for receiving transistor transistor logic (T.sup.2 L) logic level input signal includes a plurality of inverting amplifier stages. The input signal is applied to the gate electrode of a first field effect transistor in the first inverter stage and may assume a high logic level of as low as 2 volts and a low logic level of as high as 0.8 volts. In order to provide a stable switching point at the output of the first inverter stage, a feedback field effect transistor is coupled between the output of the first inverter stage and ground and has its gate electrodes coupled to a source of supply voltage (V.sub.DD). As V.sub.DD increases, the feedback field effect transistor will sink more current and thus alter the gain of the first amplifying stage to stabilize its switch point.