Patents by Inventor Richard D. Emery

Richard D. Emery has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7952190
    Abstract: A method and apparatus for fabrication of microelectronic devices are shown. In an embodiment of the invention, a microelectronic device comprises a die, the die comprising a first side, a second side, and an edge; a first plate, the first plate coupled with the die; and a package, the die being coupled with the package.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: May 31, 2011
    Assignee: Intel Corporation
    Inventor: Richard D. Emery
  • Patent number: 7531429
    Abstract: Embodiments of the invention use silicon on porous silicon wafers to produce a reduced-thickness IC device wafers. After device manufacturing, a temporary support is bonded to the device layer. The uppermost silicon layer is then separated from the silicon substrate by splitting the porous silicon layer. The porous silicon layer and temporary support are then removed and packaging is completed. Embodiments of the invention provide reliable, low cost methods and apparatuses for producing reduced-thickness IC device wafers to substantially increase thermal conductivity between the device layer of an IC device and a heat sink. In alternative embodiments, the layered silicon substrate includes an insulator layer on a layer of porous silicon and a silicon layer on the insulator layer.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Peter Tolchinsky, Irwin Yablok, Chuan Hu, Richard D. Emery
  • Patent number: 7095111
    Abstract: A package for a die includes a porous wick layer disposed between the die and a substrate. A sealed chamber between the die and substrate includes a phase-change fluid to transfer heat from a substrate side of the die to a heat spreader. Interconnects coupling bonding pads of the die to the substrate may pass through the chamber and through vias in the wick layer. In embodiments, the wick layer may have a coefficient of thermal expansion (CTE) matching a CTE of the die of the heat spreader. Heat generated by the die may evaporate the fluid in a die region and the evaporated fluid may condense in a heat spreader region. The wick layer returns the condensed fluid from the heat spreader region to the die region to complete the cycle. The fluid may be non-corrosive with respect to the interconnects and may be an electrical insulator. In embodiments, the wick layer in the heat spreader region may be disposed on the heat spreader in a pattern to efficiently draw the condensed fluid to the die region.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: August 22, 2006
    Assignee: Intel Corporation
    Inventors: Chuan Hu, Richard D. Emery
  • Patent number: 7091108
    Abstract: Embodiments of the invention use silicon on porous silicon wafers to produce a reduced-thickness IC device wafers. After device manufacturing, a temporary support is bonded to the device layer. The uppermost silicon layer is then separated from the silicon substrate by splitting the porous silicon layer. The porous silicon layer and temporary support are then removed and packaging is completed. Embodiments of the invention provide reliable, low cost methods and apparatuses for producing reduced-thickness IC device wafers to substantially increase thermal conductivity between the device layer of an IC device and a heat sink. In alternative embodiments, the layered silicon substrate includes an insulator layer on a layer of porous silicon and a silicon layer on the insulator layer.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: August 15, 2006
    Assignee: Intel Corporation
    Inventors: Peter Tolchinsky, Irwin Yablok, Chuan Hu, Richard D. Emery
  • Publication number: 20040262748
    Abstract: A method and apparatus for fabrication of microelectronic devices are shown. In an embodiment of the invention, a microelectronic device comprises a die, the die comprising a first side, a second side, and an edge; a first plate, the first plate coupled with the die; and a package, the die being coupled with the package.
    Type: Application
    Filed: June 27, 2003
    Publication date: December 30, 2004
    Applicant: Intel Corporation
    Inventor: Richard D. Emery
  • Publication number: 20040188829
    Abstract: A package for a die includes a porous wick layer disposed between the die and a substrate. A sealed chamber between the die and substrate includes a phase-change fluid to transfer heat from a substrate side of the die to a heat spreader. Interconnects coupling bonding pads of the die to the substrate may pass through the chamber and through vias in the wick layer. In embodiments, the wick layer may have a coefficient of thermal expansion (CTE) matching a CTE of the die of the heat spreader. Heat generated by the die may evaporate the fluid in a die region and the evaporated fluid may condense in a heat spreader region. The wick layer returns the condensed fluid from the heat spreader region to the die region to complete the cycle. The fluid may be non-corrosive with respect to the interconnects and may be an electrical insulator. In embodiments, the wick layer in the heat spreader region may be disposed on the heat spreader in a pattern to efficiently draw the condensed fluid to the die region.
    Type: Application
    Filed: March 31, 2003
    Publication date: September 30, 2004
    Applicant: Intel Corporation
    Inventors: Chuan Hu, Richard D. Emery