Abstract: An improved time discriminator system that is incorporated on a only a single gallium arsenide chip. The system includes a sensing stage, a ramping stage, a storage stage, a logic stage, and an output stage. An input signal is input to the sensing stage, which determines the length of successive time periods in the signal, and outputs corresponding control signals. The ramping stage generates dual ramping voltages on alternate periods of the input signal, corresponding to the successive period lengths. Values of the ramping voltages are sampled and held by a storage stage. Voltages held by the storage stage are subtracted from each other and amplified in a logic stage. The output stage resamples the signal coming from the logic stage, and outputs an analog signal that is proportional to the time difference between successive periods of the input signal.