Abstract: An alignment mark mask element protects an underlying alignment mark during subsequent processing of a fabrication substrate. The alignment mark mask element is formed concurrent with formation of a photomask from a dual-tone photoresist that exhibits a pattern reversal upon exposure to an energy level. A portion of the dual-tone photoresist above the alignment mark is exposed to an energy sufficient to reverse a positive tone resist to a negative tone, which remains above the alignment mark after developing. The remainder of the dual-tone photoresist is exposed through a reticle at a lesser energy level and patterned to define aperture locations of a photomask for formation of semiconductor device features. In addition, a photomask for use on a fabrication substrate and an intermediate semiconductor device are disclosed. Methods of forming a photomask and an intermediate semiconductor device structure are also disclosed.

Abstract: A method and apparatus are disclosed which provide a color filter array for an imaging device in which the filters of the array are accurately positioned through the use of a patterned mask layer used to form filters for one color of the array. Additionally or alternatively, the color filter array can have a light blocking spacer to block light from being transmitted between color filters and/or to a peripheral circuitry region.

Abstract: A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.

Abstract: An alignment mark mask element protects an underlying alignment mark during subsequent processing of a fabrication substrate. The alignment mark mask element is formed concurrent with formation of a photomask from a dual-tone photoresist that exhibits a pattern reversal upon exposure to an energy level. A portion of the dual-tone photoresist above the alignment mark is exposed to an energy sufficient to reverse a positive tone resist to a negative tone, which remains above the alignment mark after developing. The remainder of the dual-tone photoresist is exposed through a reticle at a lesser energy level and patterned to define aperture locations of a photomask for formation of semiconductor device features. In addition, a photomask for use on a fabrication substrate and an intermediate semiconductor device are disclosed. Methods of forming a photomask and an intermediate semiconductor device structure are also disclosed.

Abstract: A method and apparatus that provide a color filter array for use in an imaging device and/or system. The color filter array contains a stopping layer located at least on selected color filters. The stopping layer allows a planarization process step, such as a chemical mechanical planarization process step, to be carried out during the formation of the color filter array. The color filter array so formed can have a planarized surface thereon so that microlenses and/or passivation and oxide layer(s) can be directly formed on such planarized surface of the color filter array.

Abstract: An alignment mark mask element protects an underlying alignment mark during subsequent processing of a fabrication substrate. The alignment mark mask element is formed concurrent with formation of a photomask from a dual-tone photoresist that exhibits a pattern reversal upon exposure to an energy level. A portion of the dual-tone photoresist above the alignment mark is exposed to an energy sufficient to reverse a positive tone resist to a negative tone, which remains above the alignment mark after developing. The remainder of the dual-tone photoresist is exposed through a reticle at a lesser energy level and patterned to define aperture locations of a photomask for formation of semiconductor device features. In addition, a photomask for use on a fabrication substrate and an intermediate semiconductor device are disclosed. Methods of forming a photomask and an intermediate semiconductor device structure are also disclosed.

Abstract: A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.

Abstract: A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.

Abstract: An alignment mark mask element protects an underlying alignment mark during subsequent processing of the fabrication substrate. The alignment mark mask element is formed concurrent with formation of a photomask from a dual-tone photoresist that exhibits a pattern reversal upon exposure to an energy level. A portion of the dual-tone photoresist above the alignment mark is exposed to an energy sufficient to reverse a positive tone resist to a negative tone, which remains above the alignment mark after developing. The remainder of the dual-tone photoresist is exposed through a reticle at a lesser energy level and patterned to define aperture locations of a photomask for formation of semiconductor device features. In addition, a photomask for use on a fabrication substrate and an intermediate semiconductor device are disclosed. Methods of forming a photomask and an intermediate semiconductor device structure are also disclosed.

Abstract: An alignment mark mask element protects an underlying alignment mark during subsequent processing of the fabrication substrate. The alignment mark mask element is formed concurrent with formation of a photomask from a dual-tone photoresist that exhibits a pattern reversal upon exposure to an energy level. A portion of the dual-tone photoresist above the alignment mark is exposed to an energy sufficient to reverse a positive tone resist to a negative tone, which remains above the alignment mark after developing. The remainder of the dual-tone photoresist is exposed through a reticle at a lesser energy level and patterned to define aperture locations of a photomask for formation of semiconductor device features. In addition, a photomask for use on a fabrication substrate and an intermediate semiconductor device are disclosed. Methods of forming a photomask and an intermediate semiconductor device structure are also disclosed.

Abstract: An apparatus, system and method for fabricating a wafer utilizing a dual damascene process are described. A wafer-in-process, having conductive plugs within a first dielectric layer, a hard mask over the first dielectric layer, vias in a second dielectric layer which overlies the hard mask, and a photoresist material within the vias is further processed by a photolithographic device having transparent portions and radiant energy inhibiting portions. The photolithographic device is registered to the wafer-in-process to prevent radiant energy from being directly transmitted into the photoresist material overlaying the vias. This prevents the exposure of a portion of the photoresist material at a lower portion of the vias, thus protecting the hard mask layer and/or the conductive plugs from damage during a subsequent etching process. The exposed photoresist material is then removed.

Abstract: A method and system for protecting global alignment marks during the fabrication of wafers are described. A semiconductor wafer-in-process includes a substrate having one or more global alignment sites, each site having an alignment mark. A photoresist material is deposited over the wafer-in-process, including over the alignment marks. A stepper or other suitable device exposes full field images over the entire wafer-in-process, thus exposing a portion of the photoresist material covering the alignment marks which is developed. A globule of protective material is deposited over the patterned photoresist over the alignment marks, thus protecting them during a subsequent etching step. The globule of protective material can also be deposited over a portion of any other adjacent structures which need protection during etching.

Abstract: A method of designing an alignment target system to minimize lens aberrations is disclosed. A first layer alignment target's pitch is selected based on the minimum feature size of the circuit. The second layer alignment target's pitch is selected based on the diffraction pattern of the first layer's target and the illumination settings of the second layer. Displacement errors are minimized when the second layer target's 1st diffraction order overlaps the first layer target's 0th diffraction order.

Abstract: An apparatus, system and method for fabricating a wafer utilizing a dual damascene process are described. A wafer-in-process, having conductive plugs within a first dielectric layer, a hard mask over the first dielectric layer, vias in a second dielectric layer which overlies the hard mask, and a photoresist material within the vias is further processed by a photolithographic device having transparent portions and radiant energy inhibiting portions. The photolithographic device is registered to the wafer-in-process to prevent radiant energy from being directly transmitted into the photoresist material overlaying the vias. This prevents the exposure of a portion of the photoresist material at a lower portion of the vias, thus protecting the hard mask layer and/or the conductive plugs from damage during a subsequent etching process. The exposed photoresist material is then removed.

Abstract: An alignment mark mask element protects an underlying alignment mark during subsequent processing of the fabrication substrate. The alignment mark mask element is formed concurrent with formation of a photomask from a dual-tone photoresist that exhibits a pattern reversal upon exposure to an energy level. A portion of the dual-tone photoresist above the alignment mark is exposed to an energy sufficient to reverse a positive tone resist to a negative tone, which remains above the alignment mark after developing. The remainder of the dual-tone photoresist is exposed through a reticle at a lesser energy level and patterned to define aperture locations of a photomask for formation of semiconductor device features. In addition, a photomask for use on a fabrication substrate and an intermediate semiconductor device are disclosed. Methods of forming a photomask and an intermediate semiconductor device structure are also disclosed.

Abstract: An apparatus, system and method for fabricating a wafer utilizing a dual damascene process are described. A wafer-in-process, having conductive plugs within a first dielectric layer, a hard mask over the first dielectric layer, vias in a second dielectric layer which overlies the hard mask, and a photoresist material within the vias is further processed by a photolithographic device having transparent portions and radiant energy inhibiting portions. The photolithographic device is registered to the wafer-in-process to prevent radiant energy from being directly transmitted into the photoresist material overlaying the vias. This prevents the exposure of a portion of the photoresist material at a lower portion of the vias, thus protecting the hard mask layer and/or the conductive plugs from damage during a subsequent etching process. The exposed photoresist material is then removed.

Abstract: A stepper device and method of using the stepper device in which a light source in the stepper generates an annular or multipole pattern of light having a relatively large coherency value that is used to expose inner fields of a photoresist-coated wafer. The light source generates an annular or multipole pattern of light having a relatively small coherency that is used to expose outer fields of the wafer adjacent its edge. The use of light having a relatively small coherence value to expose the outer fields of the wafer causes the exposure width of isolated features to be relatively large compared to the exposure width of dense features. As a result, after etching, the isolated features and the dense features can have the same width since etching is more effective for dense features.

Abstract: A method of designing an alignment target system to minimize lens aberrations is disclosed. A first layer alignment target's pitch is selected based on the minimum feature size of the circuit. The second layer alignment target's pitch is selected based on the diffraction pattern of the first layer's target and the illumination settings of the second layer. Displacement errors are minimized when the second layer target's 1st diffraction order overlaps the first layer target's 0th diffraction order.

Abstract: A method of designing an alignment target system to minimize lens aberrations is disclosed. A first layer alignment target's pitch is selected based on the minimum feature size of the circuit. The second layer alignment target's pitch is selected based on the diffraction pattern of the first layer's target and the illumination settings of the second layer. Displacement errors are minimized when the second layer target's 1st diffraction order overlaps the first layer target's 0th diffraction order.

Abstract: A method of designing an alignment target system to minimize lens aberrations is disclosed. A first layer alignment target's pitch is selected based on the minimum feature size of the circuit. The second layer alignment target's pitch is selected based on the diffraction pattern of the first layer's target and the illumination settings of the second layer. Displacement errors are minimized when the second layer target's 1st diffraction order overlaps the first layer target's 0th diffraction order.