Abstract: An on-demand table model for semiconductor device evaluation is provided. A method of providing on-demand table models for semiconductor device evaluation, includes measuring one or more measurement values of an instance of a semiconductor device. The method further includes providing, by a processor, a table model of the instance for the semiconductor device evaluation upon receiving a request for the semiconductor device evaluation. The method further includes generating a table entry in the table model for the one or more measurement values, the table entry including one or more evaluation values of an evaluation function for the instance.

Abstract: An on-demand table model for semiconductor device evaluation is provided. A method of providing on-demand table models for semiconductor device evaluation, includes measuring one or more measurement values of an instance of a semiconductor device. The method further includes providing, by a processor, a table model of the instance for the semiconductor device evaluation upon receiving a request for the semiconductor device evaluation. The method further includes generating a table entry in the table model for the one or more measurement values, the table entry including one or more evaluation values of an evaluation function for the instance.

Abstract: A method and a system for validating initial conditions (ICs) generally provided by a user when simulating a VLSI circuit are described. Inconsistent ICs sets are detected and replaced by consistent subsets thereof. The method selects the resistance and source values in a Norton or Thevenin circuit used to enforce the IC, and detects when specified ICs are inconsistent while preserving critical or fragile ICs when a two DC-pass approach is used. It further correlates the set of consistent ICs thus obtained with an equivalent circuit and simultaneously provides an input for future use. This allows a user to be notified and given a measure of how bad the inconsistencies are. Detecting inconsistencies is achieved either by measuring the holding current or by measuring the voltage drift if the two DC-pass approach is used.

Abstract: A system and method for designing a structure such as a circuit. First the sensitivity of a circuit performance function (sensitivity data set - SDS) to at least one physical parameter is determined. Then, an estimated distribution of the design function calculated by using the SDS and random parameter values. Subsequently, the parameters corresponding to the estimated distribution was used to accurately calculate the tail. The tail is compared to a predetermined design objectives. If the objectives are not met, the design is modified and the calculation steps repeated until the design objectives are met.

Abstract: The present invention relates to an improved method for computer-aided electrical circuit simulation which combines circuit partitioning, modified nodal formulation and conjugate-gradient solution method to efficiently analyze large electrical circuit networks. Circuit partitioning is used to create sub-circuits which isolate the passive elements of the electrical circuit. Modified nodal formulation is used to formulate matrices representative of the resultant sub-circuits. All matrices resulting from the sub-circuits containing only passive elements will be positive-definite symmetric and are efficiently solved using conjugate gradient method. Conjugate-gradient method is known to be an extremely efficient method for solving matrices of this type.

Abstract: A read only memory utilizing a two-level cascoded current steering approach feeding a two-level common base isolation and sense amplifier network. The isolation network allows formation of a multi-way collector dot without deleterious effect upon the high speed current sensing operation. Single transistor cells with a common subcollector bed and common base rails as word lines make up the highly dense high speed array. The current source is provided by a current mirror circuit. The common-base, low impedance sense amplifier converts the sense current signal into a voltage swing which is then fed to the off-chip driver circuit via an emitter-follower pre-driver stage.