Abstract: A system for and a method of generating a four phase clock signal is disclosed. The system includes an oscillator circuit that generates a clocking signal of frequency F. A flip-flop, under control of a Master Clear signal, establishes the first stage of a shift register in an active state while the clocking signal drives the shaft register to serial, end-around, shift the active state through the shift register. The parallel outputs of the shift register are coupled to respectively associated pulse generators which are also triggered by the clock signal to emit the four phase clock signal therefrom. The method ensures that the first phase signal is always the first signal to be emitted from the system while compatible semiconductor circuitry is used throughout and is operated at or near the frequency limit of the semiconductor circuitry used.