Abstract: A multifunction access circuit for use with first and second digital computers each having an address bus for supplying addresses and a data bus for supplying data. The access circuit has an address decoder with inputs for the address bus from the first computer, and an address translator circuit having address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers selectable by the address decoder and data inputs to program the registers so selected with data from the data bus from the first computer. Also in the access circuit is a port circuit with registers controlled by the address decoder for entry of address information from the data bus of the first computer and assertion of the address information on the address bus of the second computer.

Abstract: A graphics display system includes a random access memory arranged with a split serial register and a multiplexer for coupling column of storage cells from the memory array to storage elements of the split serial register. Data stored in either a low half or a high half of the addresses of the memory array may be selectively coupled through the multiplexer to either a low half or a high half of the split serial register. For a tile oriented graphics display operation, this arrangement increases the number of choices of where within the random access memory array to store specific bits of the tile data to be displayed. Data representing a tile can be mapped into a single row of the random access memory array.

Abstract: A three input arithmetic logic unit (230) forms a mixed arithmetic and Boolean combination of three multibit input signals. The current instruction drives an instruction decoder (250, 245) that generates functions signals F0-F7 which control the combination formed. The three input arithmetic logic unit (230) preferably employs a set of bit circuits (400), each forming carry propagate, generate and kill signals. These signals and a carry input produce a bit resultant and a carry output to the next bit circuit. Selection of the function signals enables the combination to be insensitive to one of the input signals, thus performing a two input function of remaining input signals. The instruction itself may include the function signals and function modification bits, or the function signals and function modification signals may be stored in a special data register. Function modification signals cause modification of the function signals prior to use.

Abstract: A multiplier (220) selectively multiplies either a pair of 2N bit digital numbers or two pair of N bit digital numbers. The multiplier (220) includes a first input encoding circuit (350), a second input encoding circuit (352), a number of partial product generators (353, 354, 356, 363, 364, 366) and a set of adders (355, 357, 365, 367, 368, 369). The first input encoder circuit (350) generates partial product control signals from a first data word holding either a first 2N bit number or a first pair of N bit numbers. The second input encoding circuit (352) generates partial product input signals to the partial product generators (353, 354, 356, 363, 364, 366) from a second data word holding either a second 2N bit number or a second pair of N bit numbers. A first set of adders (355, 357) forms a weighted first sum of the first set of partial products signals. A second set of adders (365, 367) forms a weighted second sum of said second set of partial product signals.

Abstract: A processing system operating on data words having first and second portions includes a memory bank comprising first and second memories each with associated first and second set of address inputs. First memory includes a first storage location storing the first portion of a first word accessible by a set of address bits received at the first inputs and a second set of address bits received at the second inputs. The first memory further includes a second storage location storing the second portion of a second word accessible by the first set of bits received at the first inputs and a third set of bits received at the second inputs. Second memory includes a first storage location storing the second portion of the second word accessible by the first set of bits received at the first inputs and the second set of bits received at the second inputs.

Abstract: A computer graphics system. The system includes a video memory having a shift register adapted for split shift register transfers, and digital computer for controlling the video memory and having a tap point counter clocked by a shift clock signal and also having a blanking circuit with a blanking output. Further, logic circuitry enabled by the blanking output is connected to initiate an extra shift clock pulse for the tap point counter during a blanking interval. Other systems, palette devices, and methods are also disclosed.

Abstract: Method and apparatus of providing a display on a raster-scanned screen (1) from data stored in a video random access memory (8) having row and column addresses (6,7) for the storage elements, wherein the display area of the screen (1) is divided into a plurality of identical rectangular areas or "tiles". Addressing of the video random access memory (8) is derived by converting the screen raster-scanning signals via conversion circuits (5) such that sequential addressing of entire rows of storage elements of the video random access memory (8) corresponds to a description of all of the rectangular areas in turn, wherein the number of rectangular areas across the screen width is not equal to an integral power of 2.

Abstract: A circuit and method of operation for controlling block-write operations to interleaved memories is disclosed which includes first and second interleave banks of memories, each memory addressable in a normal mode in a block-write mode. Each memory has a plurality of input nodes for receiving data in a normal mode, ones of the input nodes operable to receive data in the block-write mode and other ones of said input nodes not used in the block-write mode. Coupling circuitry couples leads from an output bus to input nodes of the first bank memories which are operable to receive data in the block-write mode and to input nodes in the second bank of memories which are not used in the block-write mode.

Abstract: A video random access memory includes memory cells arranged in rows and columns. The columns of memory cells are divided into first and second portions, and the cells of each row of the first portion of memory are interleaved by address with the cells of the same row of the second portion of memory. A first half of a serial register includes a plurality of storage elements that are interleaved by address with a plurality of storage elements of a second half of the serial register. Between the first and second portions of the memory cells, column leads and a multiplexer selectively couple data from either the first portion or the second portion of the columns of the memory cells to either the first half or the second half of the serial register.

Abstract: A circuit controls the reordering of data as it is transferred to control a memory. The data to be reordered is presented such that the ordinate bit position within a data word is uniquely associated with a particular input to a data bus. The bus inputs, however, are connected to the VRAM in an arrangement contrary to the desired ordinate association with the compressed data word. A single swizzle logic circuit operates to allow graphic compressed data to be reordered for presentation to the block-write inputs of a VRAM regardless of the VRAM or pixel size. The circuit relies upon properly expanding the compressed data prior to the actual reordering of the ordinate positions of the data bits. A method for controlling the reordering of data also is described.

Abstract: A digital data storage circuit for a digital signal processor which is capable of receiving asynchronous inputs and is such as to be testable by selectively configuring the storage circuits as a shift register enabling the entry and extraction of test data into the processor. The storage circuit includes two latch elements each formed by two complementary transistor inverter circuits connected in a positive feedback arrangement and in which the output current capability of the second inverter circuit is restricted to enable the latch element to change state in response to input signals applied to it. Asynchronous inputs are applied to a first latch element through switch means comprising a complementary transistor inverter responsive to a SET input in series with a transistor responsive to a CLEAR input. The complementary inverter is connected to the input of the first latch element through a series connected transistor.

Abstract: A read-only memory suitable for use as the control ROM of a microprocessor has each output line divided into first and second parts. Memory elements connected to the first parts are responsive to early-occurring input signals and memory elements connected to the second parts are responsive to late-occurring input signals. Switch means are provided to enable the output signals from the second parts of the output lines to be generated in response to a late-occurring input signal independently of the loading of the memory elements connected to the first parts of the output lines.

Abstract: A clock generating circuit for use in a signal processing circuit to enable it to be synchronized with other circuits in response to a reset signal uses a multi-state circuit which is cyclically stepped through its states by a clock drive signal and a decoder responsive to the state of the multi-state circuit to produce the required clock pulses. The reset signal is used to stop the multi-state circuit at a particular state and hold it there for a period of time enabling other similar clock pulse generating circuits to reach the same state and be held there. At the end of the period of time the multi-state circuits resume their cyclic stepping with all the circuits in synchronism.

Abstract: A digital data storage circuit for a digital signal processor which is capable of receiving asynchronous inputs and is such as to be testable by selectively configuring the storage circuits as a shift register enabling the entry and extraction of test data in the processor. The storage circuit includes two latch elements each formed by two complementary transistor inverter circuits connected in a positive feedback arrangement and in which the output current capability of the second inverter circuit is restricted to enable the latch element to change state in response to input signals applied to it. Asynchronous inputs are applied to a first latch element through switch means comprising a complementary transistor inverter responsive to a SET input in series with a transistor responsive to a CLEAR input. The complementary inverter is connected to the input of the first latch element through a series connected transistor.

Abstract: A binary adder circuit is described using dynamic transistor logic in which for high speed carry propagation the adder stages are grouped in pairs or larger numbers and additional dynamic logic means is provided in each group to control a single transistor connected in series in the carry propagation path over the group. The transistors used in the specific embodiments are MOS transistors, but some or all of these could be replaced by junction FET's or bipolar transistors.

Abstract: The position of an end "1" bit in an input number is detected by applying the inverted bits in parallel to inputs of respective NOR gates (61 to 68), the other inputs of which are connected to the nodes of a chain of dynamic field effect transistors (A1 to A8) along which a "O" is propagated. The coincidence of two O's at the inputs of a NOR gate causes it to produce a "1" output representing the location of the end "1" of the input number. The outputs of the NOR gates (L1 to L8) are connected to the column conductors of an field effect transistor array (LA) which produces on the row conductors array in parallel, inverted, binary coded form a number corresponding to the position of the NOR gate producing a "1" output. The apparatus may be divided into several units (U1 to U4) responsive to adjacent groups of the bits of the input number each producing a representation of the location of the end "1" in its group.

Abstract: A CMOS random access memory has storage elements (1, 2 and 3) which produce complementary outputs on a pair of output conductors (7, 8). In order to speed up the establishment of the output voltages on the conductors two cross-connected transistors (22, 23) are provided to supplement the discharging of that conductor which is to have the lower voltage, each transistor being responsive to the voltage on one conductor to discharge the other conductor. The correct timing of the operation of the cross-connected transistors is provided by two further transistors (26, 27) having their gates respectively connected to the conductors which are arranged to become conducting when an adequate voltage charge has been achieved by the storage element. When either of the further transistors conducts a transistor (24) in series with the two cross-connected transistors is turned on to enable them to operate.

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program and data memory, with separate address and data paths for program and data. An external program address bus allows off-chip program fitch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension. The on-chip program memory may be a RAM and this additional RAM may be configured as either program or data memory space.

Abstract: An overvoltage detector circuit for connection to an input terminal of a microcomputer device or the like employs a bistable latch with two inputs, one connected to a reference potential and the other to the input terminal. When the inputs are gated, the latch flips to one state if the terminal is at an overvoltage, or the other state if the terminal is at zero or logic-1. This circuit may be used to institute a test mode for the microcomputer.

Abstract: A system for real-time digital processing employs a single-chip microcomputer device having a high-speed on-chip program ROM and a separate data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension. The on-chip program ROM has a low-level precharge circuit with feedback to improve speed or access time.