Abstract: A tree data structure with range-specifying keys and associated methods. In one embodiment, the data structure is a tree that is stored in a machine readable medium. Each key has two values that define a range and has an associated data item that is associated with the range. Various embodiments of processes to search the tree, add ranges and keys to the tree, delete ranges and keys from the tree, and to generally maintain the tree data structure are disclosed.

Abstract: Methods and apparatus are presented for unobtrusively monitoring processor states and characterizing bottlenecks in an arbitrary customer workload. An instruction queue and an instruction control unit within a pipelined central processor unit (CPU) provide for grouping and issuing multiple instructions per clock cycle for overlapped execution. Additionally, instruction and data caches in operation with integer and floating point function units issue a program counter to the instruction cache, which subsequently supplies instructions to integer and floating point instruction queues. Both integer and floating point unit datapaths comprise fetch, decode, execute, and writeback stages. In the preferred embodiment, ten additional datalines transmitting PIPE signals are routed from the integer and floating point function units to contact pins on an external pin gate array supporting the CPU.

Abstract: In a pipelined processor, an instruction queue and an instruction control unit is provided to group and issue m instructions simultaneously per clock cycle for execution. An integer and a floating point function unit capable of generating n.sub.1 and n.sub.2 integer and floating point results per clock cycle respectively, where n.sub.1 and n.sub.2 are sufficiently large to support m instructions being issued per clock cycle, is also provided to complement the instruction queue and instruction control unit. The pipeline stages are divided into integer and floating point pipeline stages where the early floating point stages overlap with the later integer pipeline stages. The instruction queue stores sequential instructions of a program and target instructions of a branch instruction of the program, fetched from the instruction cache.