Patents by Inventor Richard David Price

Richard David Price has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210074563
    Abstract: The invention relates to a system for manufacturing a plurality of integrated circuits, IC, mounted on a common support, the system comprising: an input station configured (adapted, arranged) to receive at least one common support; an output station configured (adapted, arranged) to receive at least one common support having a plurality of integrated circuits formed thereon; a plurality of processing modules each module being operable (configured, arranged, adapted) to perform at least one of the processing steps (e.g. deposition, patterning, etching) for forming an integrated circuit on the common support; a transfer means operable (configured, arranged, adapted) to transfer the at least one common support from the input station to the output station and to one or more of the processing modules therebetween; control means (e.g.
    Type: Application
    Filed: January 30, 2019
    Publication date: March 11, 2021
    Inventors: Richard David PRICE, Neil DAVIES, Scott WHITE, Thomas Stanley VAN DEN HEEVER, Kenneth David WILLIAMSON, Nathaniel James GREEN
  • Patent number: 10811383
    Abstract: A method of manufacturing a plurality of electronic circuits is disclosed. Each electronic circuit comprises a respective first portion, comprising a respective group of contact pads, and a respective integrated circuit, IC, comprising a respective group of terminals and mounted on the respective group of contact pads with each terminal in electrical contact with a respective contact pad. The method comprises: providing a first structure comprising the plurality of first portions; providing a second structure comprising the plurality of ICs and a common support arranged to support the plurality of ICs; transferring said ICs from the common support onto a first roller; transferring said ICs from the first roller onto a second roller; and transferring said ICs from the second roller onto the first structure such that each group of terminals is mounted on a respective group of contact pads.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: October 20, 2020
    Assignee: PRAGMATIC PRINTING LTD.
    Inventors: Neil Davies, Richard David Price, Stephen Devenport, Stuart Philip Speakman
  • Publication number: 20190067243
    Abstract: A method of manufacturing a plurality of electronic circuits is disclosed. Each electronic circuit comprises a respective first portion, comprising a respective group of contact pads, and a respective integrated circuit, IC, comprising a respective group of terminals and mounted on the respective group of contact pads with each terminal in electrical contact with a respective contact pad. The method comprises: providing a first structure comprising the plurality of first portions; providing a second structure comprising the plurality of ICs and a common support arranged to support the plurality of ICs; transferring said ICs from the common support onto a first roller; transferring said ICs from the first roller onto a second roller; and transferring said ICs from the second roller onto the first structure such that each group of terminals is mounted on a respective group of contact pads.
    Type: Application
    Filed: February 9, 2017
    Publication date: February 28, 2019
    Inventors: Neil DAVIES, Richard David PRICE, Stephen DEVENPORT, Stuart Philip SPEAKMAN
  • Patent number: 10020377
    Abstract: A method of manufacturing an electronic device comprising a first terminal (e.g. a source terminal), a second terminal (e.g. a drain terminal), a semiconductor channel connecting the first and second terminals and a gate terminal to which a potential may be applied to control a conductivity of the channel. The method comprises a first exposure of a photoresist from above the substrate using a mask and a second exposure from below, wherein in the second exposure the first and second terminals shield a part of the photoresist from exposure. An intermediate step reduces the solubility of the photoresist exposed in the first exposure. A window is formed in the photoresist at the location which was shielded by the mask, but exposed to radiation from below. Semiconductor material, dielectric material and conductor material are deposited inside the window to form a semiconductor channel, gate dielectric, and a gate terminal, respectively.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: July 10, 2018
    Assignee: Pragmatic Printing Limited
    Inventors: John James Gregory, Richard David Price
  • Publication number: 20170278945
    Abstract: A method of manufacturing an electronic device comprising a first terminal (e.g. a source terminal), a second terminal (e.g. a drain terminal), a semiconductor channel connecting the first and second terminals and a gate terminal to which a potential may be applied to control a conductivity of the channel. The method comprises a first exposure of a photoresist from above the substrate using a mask and a second exposure from below, wherein in the second exposure the first and second terminals shield a part of the photoresist from exposure. An intermediate step reduces the solubility of the photoresist exposed in the first exposure. A window is formed in the photoresist at the location which was shielded by the mask, but exposed to radiation from below. Semiconductor material, dielectric material and conductor material are deposited inside the window to form a semiconductor channel, gate dielectric, and a gate terminal, respectively.
    Type: Application
    Filed: November 7, 2016
    Publication date: September 28, 2017
    Applicant: Pragmatic Printing Ltd
    Inventors: John James Gregory, Richard David Price
  • Patent number: 9601597
    Abstract: A method of manufacturing a substantially planar electronic device is disclosed. The method employs a resist having three different thicknesses used for defining different structures in a single masking step. Exemplary structures are substantially planar transistors having side-gates and diodes.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: March 21, 2017
    Assignee: Pragmatic Printing Limited
    Inventors: Antony Colin Fryer, Richard David Price
  • Patent number: 9520481
    Abstract: A method of manufacturing an electronic device comprising a first terminal (e.g. a source terminal), a second terminal (e.g. a drain terminal), a semiconductor channel connecting the first and second terminals and a gate terminal to which a potential may be applied to control a conductivity of the channel. The method comprises a first exposure of a photoresist from above the substrate using a mask and a second exposure from below, wherein in the second exposure the first and second terminals shield a part of the photoresist from exposure. An intermediate step reduces the solubility of the photoresist exposed in the first exposure. A window is formed in the photoresist at the location which was shielded by the mask, but exposed to radiation from below. Semiconductor material, dielectric material and conductor material are deposited inside the window to form a semiconductor channel, gate dielectric, and a gate terminal, respectively.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: December 13, 2016
    Assignee: Pragmatic Printing Limited
    Inventors: John James Gregory, Richard David Price
  • Patent number: 9263553
    Abstract: A transistor includes a substrate, a source terminal and a drain terminal, each terminal being supported by the substrate, and the source and drain terminal being separated by a portion of the substrate, a layer of semiconductive material deposited so as to cover the portion of the substrate and to connect the source terminal to the drain terminal, a layer of dielectric material deposited so as to cover at least a portion of the layer of semiconductive material, and a layer of electrically conductive material deposited so as to cover at least a portion of the layer of dielectric material. The layer of electrically conductive material providing a gate terminal to which a potential may be applied to control a conductivity of the layer of semiconductive material connecting the source and drain terminals.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: February 16, 2016
    Assignee: Pragmatic Printing Limited
    Inventor: Richard David Price
  • Publication number: 20160020299
    Abstract: A method of manufacturing an electronic device comprising a first terminal (e.g. a source terminal), a second terminal (e.g. a drain terminal), a semiconductor channel connecting the first and second terminals and a gate terminal to which a potential may be applied to control a conductivity of the channel. The method comprises a first exposure of a photoresist from above the substrate using a mask and a second exposure from below, wherein in the second exposure the first and second terminals shield a part of the photoresist from exposure. An intermediate step reduces the solubility of the photoresist exposed in the first exposure. A window is formed in the photoresist at the location which was shielded by the mask, but exposed to radiation from below. Semiconductor material, dielectric material and conductor material are deposited inside the window to form a semiconductor channel, gate dielectric, and a gate terminal, respectively.
    Type: Application
    Filed: February 13, 2013
    Publication date: January 21, 2016
    Applicant: Pragmatic Printing Ltd
    Inventors: John James Gregory, Richard David Price
  • Patent number: 9018096
    Abstract: A method of manufacturing a structure comprising substantially planar electronic devices comprises providing an active material layer having a plurality of insulative features formed therein. The features at least partly inhibit electrical current flow and define at least a first substantially planar electronic device in the layer having at least first and second terminals comprising an area of the active material layer. A patterned dielectric layer having an exposed surface patterned with at least a first depression arranged over the first terminal is formed over the active material layer. Dielectric material is removed from at least a base of the first depression to expose a first terminal surface and form a hole through the dielectric material to the first terminal. The hole is at least partly filled with electrically conductive material to form an electrical connection to the first terminal. Corresponding structures and electrical circuits are also described and claimed.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: April 28, 2015
    Assignee: Pragmatic Printing Ltd.
    Inventors: Richard David Price, Ian Barton
  • Publication number: 20150001597
    Abstract: A method of manufacturing a substantially planar electronic device is disclosed. The method employs a resist having three different thicknesses used for defining different structures in a single masking step. Exemplary structures are substantially planar transistors having side-gates and diodes.
    Type: Application
    Filed: February 21, 2013
    Publication date: January 1, 2015
    Applicant: PRAGMATIC PRINTING LIMITED
    Inventors: Antony Colin Fryer, Richard David Price
  • Publication number: 20130020643
    Abstract: A transistor includes a substrate, a source terminal and a drain terminal, each terminal being supported by the substrate, and the source and drain terminal being separated by a portion of the substrate, a layer of semiconductive material deposited so as to cover the portion of the substrate and to connect the source terminal to the drain terminal, a layer of dielectric material deposited so as to cover at least a portion of the layer of semiconductive material, and a layer of electrically conductive material deposited so as to cover at least a portion of the layer of dielectric material. The layer of electrically conductive material providing a gate terminal to which a potential may be applied to control a conductivity of the layer of semiconductive material connecting the source and drain terminals.
    Type: Application
    Filed: March 29, 2011
    Publication date: January 24, 2013
    Inventor: Richard David Price
  • Publication number: 20120153502
    Abstract: A method of manufacturing a structure comprising substantially planar electronic devices comprises providing an active material layer having a plurality of insulative features formed therein. The features at least partly inhibit electrical current flow and define at least a first substantially planar electronic device in the layer having at least first and second terminals comprising an area of the active material layer. A patterned dielectric layer having an exposed surface patterned with at least a first depression arranged over the first terminal is formed over the active material layer. Dielectric material is removed from at least a base of the first depression to expose a first terminal surface and form a hole through the dielectric material to the first terminal. The hole is at least partly filled with electrically conductive material to form an electrical connection to the first terminal. Corresponding structures and electrical circuits are also described and claimed.
    Type: Application
    Filed: September 2, 2010
    Publication date: June 21, 2012
    Inventors: Richard David Price, Ian Barton
  • Patent number: 7303824
    Abstract: An electroluminescent device which has an electroluminescent layer formed of a binuclear, trinuclear or polynuclear rare earth organic complex in which the metals are linked through a bridging ligand.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: December 4, 2007
    Assignee: OLED-T Limited
    Inventors: Poopathy Kathirgamanathan, Lisa Marie Bushby, Richard David Price
  • Publication number: 20040253477
    Abstract: An electroluminescent device which has an electroluminescent layer formed of a binuclear, trinuclear or polynuclear rare earth organic complex in which the metals are linked through a bridging ligand.
    Type: Application
    Filed: April 19, 2004
    Publication date: December 16, 2004
    Inventors: Poopathy Kathirgamanathan, Lisa Marie Bushby, Richard David Price
  • Patent number: 5996722
    Abstract: A tractor (1) has front wheels (2), rear wheels (3) and carries an implement (7, 10) by a linkage (8) or tows a trailer (11). The front wheels (2) are steered normally by a steering wheel (6). The rear wheels (3) can be held in fixed alignment or they can be steered in various selectable modes, being slaved to the front wheels. In one mode, they are turned in the opposite direction to the front wheels, to give a very tight turning circle. In another mode, they turn with the front wheels but to a lesser degree, governed by the tractor wheel base (A) and the distance (B) of this implement behind the tractor, to keep lateral forces on the implement to a minimum. There can be automatic changeover between modes of steering.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: December 7, 1999
    Inventor: Richard David Price