Abstract: The invention relates to new bicyclic heterocyclic derivative compounds, to pharmaceutical compositions comprising said compounds and to the use of said compounds in the treatment of diseases, e.g. cancer.

Abstract: The invention relates to new bicyclic heterocyclic derivative compounds of Formula (I), to pharmaceutical compositions comprising said compounds and to the use of said compounds in the treatment of diseases, e.g. cancer The compounds of Formula (I) are inhibitors of FGFR, VEGFR or PDGFR.

Abstract: The present invention pertains to certain imidazo[4,5-b]pyridin-2-one and oxazolo[4,5-b]pyridin-2-one compounds and analogs thereof, which, inter alia, inhibit RAF (e.g., B-RAF) activity, inhibit cell proliferation, treat cancer, etc.

Abstract: A video controller includes a video block that connects to the print control engine and one laser driver. The video block includes a direct memory access (DMA) block, a video processor, a waveform generator including pattern and multiple pulse mode modulation, a frequency synthesizer, configuration registers, and a data bus. The frequency synthesizer connects to the waveform generator. The configuration registers connect to the DMA block, video processor and the waveform generator. The data bus, operative to carry bus control signals, connects the DMA block, video processor, waveform generator, and the configuration registers.

Abstract: A digital circuit generates very precise varying clock frequencies for applications that can tolerate a small degree of jitter but require exact longer term frequencies, e.g. a video clock for a laser printer. Some subpixel jitter is acceptable, but the overall pixel rate remains exact and consistent. In some applications, the jitter may be desirable to smear the EMI spectrum. For example, if the high frequency input clock is modulated, the edges of the video clock will also be modulated yet remain within the jitter and frequency specification.

Abstract: A printer includes a direct memory access controller (DMA), a video processor, and a video signal generator. A frequency synthesizer connects to the video signal generator. Configuration registers bidirectionally connect to the DMA, video processor, the video signal generator and the frequency synthesizer. A data bus electrically connects the DMA and the configuration registers.

Abstract: Embodiments of the present invention are described in an integrated circuit. The integrated circuit comprises circuit elements configured to be clocked via an oscillating signal, and a detector. The detector is configured to detect a state of the oscillating signal and provide a detection signal indicative of the state of the oscillating signal. The detector comprises a first delay line configured to provide a first delayed signal to logic that provides the detection signal.

Abstract: Embodiments of the present invention provide an integrated circuit. In one embodiment, the integrated circuit comprises logic blocks and a measurement circuit. The measurement circuit is configured to measure internal operating parameters of the integrated circuit to obtain operating parameter data and provide the operating parameter data for evaluation and configuration of the integrated circuit and the logic blocks.

Abstract: A digital circuit generates very precise varying clock frequencies for applications that can tolerate a small degree of jitter but require exact longer term frequencies, e.g. a video clock for a laser printer. Some subpixel jitter is acceptable, but the overall pixel rate remains exact and consistent. In some applications, the jitter may be desirable to smear the EMI spectrum. For example, if the high frequency input clock is modulated, the edges of the video clock will also be modulated yet remain within the jitter and frequency specification.

Abstract: Embodiments of the present invention provide an integrated circuit. In one embodiment, the integrated circuit comprises logic blocks, a measurement circuit and a control circuit. The measurement circuit is configured to measure operating parameters of the integrated circuit and the logic blocks and provide operating parameter data. The control circuit is configured to receive the operating parameter data, evaluate the operating parameter data to obtain configuration data and configure the integrated circuit with the configuration data.

Abstract: Embodiments of the present invention provide an integrated circuit. In one embodiment, the integrated circuit comprises logic blocks and a measurement circuit. The measurement circuit is configured to measure internal operating parameters of the integrated circuit to obtain operating parameter data and provide the operating parameter data for evaluation and configuration of the integrated circuit and the logic blocks.

Abstract: Embodiments of the present invention provide an integrated circuit. In one embodiment, the integrated circuit comprises logic blocks, a measurement circuit and a control circuit. The measurement circuit is configured to measure operating parameters of the integrated circuit and the logic blocks and provide operating parameter data. The control circuit is configured to receive the operating parameter data, evaluate the operating parameter data to obtain configuration data and configure the integrated circuit with the configuration data.

Abstract: A system and method for emulating an ASIC using multiple filed programmable gate arrays. A designer, using this method, emulates an integrated circuit design using a prototyping apparatus. The method includes reserving more than one location in a prototyping apparatus for a circuit block that is part of an ASIC design. Each of the reserved locations is coupled to a single interconnection point within the prototyping apparatus. By reserving more than one space for the possible locations of each circuit block, a designer can choose late in the design process where to finally place each circuit block, thereby allowing for design changes without problematic resynthesis and communication path reroutes.

Abstract: Embodiments of the present invention are described in an integrated circuit. The integrated circuit comprises circuit elements configured to be clocked via an oscillating signal, and a detector. The detector is configured to detect a state of the oscillating signal and provide a detection signal indicative of the state of the oscillating signal. The detector comprises a first delay line configured to provide a first delayed signal to logic that provides the detection signal.