Patents by Inventor Richard Dean Putman

Richard Dean Putman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for selecting a compatibility mode of operation for a lamp assembly
    Patent number: 8933648
    Abstract: According to systems and methods of this disclosure, a controller may be configured to: operate in a first compatibility mode of operation, determine from an input signal of the lamp assembly during operation in the first compatibility mode whether the first compatibility mode of operation provides compatibility between the lamp assembly and a power infrastructure to which it is coupled, select the first compatibility mode of operation from a plurality of modes of operation as a compatibility mode responsive to determining that the first compatibility mode of operation provides compatibility between the lamp assembly and a power infrastructure to which it is coupled, and select a second compatibility mode of operation from the plurality of modes of operation as the compatibility mode responsive to determining that the first compatibility mode of operation does not provide compatibility between the lamp assembly and the power infrastructure to which it is coupled.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: January 13, 2015
    Assignee: Cirrus Logic, Inc.
    Inventors: Richard Dean Putman, Yanhui Xie, Michael Kost, Jean Charles Pina
  • Methods for forming area-efficient scan chains in integrated circuits, and integrated circuits embodying the same
    Patent number: 7971170
    Abstract: A method of forming a scan chain for testing an integrated circuit includes examining an interconnection of register elements in an integrated circuit design. A register element segment is identified which includes a source register element having an output and a destination register element having an input directly coupled to the output of the source register element. The segment is selectively coupled to another scan register element to form a portion of scan chain.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: June 28, 2011
    Assignee: Cirrus Logic, Inc.
    Inventors: Bruce Eliot Duewer, Richard Dean Putman
  • Methods for forming area-efficient scan chains in integrated circuits, and integrated circuits embodying the same
    Publication number: 20080195991
    Abstract: A method of forming a scan chain for testing an integrated circuit includes examining an interconnection of register elements in an integrated circuit design. A register element segment is identified which includes a source register element having an output and a destination register element having an input directly coupled to the output of the source register element. The segment is selectively coupled to another scan register element to form a portion of scan chain.
    Type: Application
    Filed: April 9, 2008
    Publication date: August 14, 2008
    Inventors: Bruce Ellot Duewer, Richard Dean Putman
  • Methods for forming area-efficient scan chains in integrated circuits, and integrated circuits embodying the same
    Patent number: 7376915
    Abstract: A method of forming a scan chain for testing an integrated circuit includes examining an interconnection of register elements in an integrated circuit design. A register element segment is identified which includes a source register element having an output and a destination register element having an input directly coupled to the output of the source register element. The segment is selectively coupled to another scan register element to form a portion of scan chain.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: May 20, 2008
    Assignee: Cirrus Logic, Inc.
    Inventors: Bruce Eliot Duewer, Richard Dean Putman