Abstract: A semiconductor non-volatile memory device, particularly a flash memory array, having a chip configuration with a plurality of pins including a write protect pin, a serial in pin and an optional parallel data bus with input-output pins (I/O7-0), plus other pins, all electrically communicating with the memory array and particularly a sector protection register of variable size and location. The sector protection register defines which sectors or group of sub-sectors to protect and is controlled by the use of commands via the serial in pin or the optional input-output pins. The sector protection may be selectably controlled by either use of a signal to the write protect pin or use of commands via the serial in pin or the optional input-output pins to the command and control logic. A logic circuit instantly determines whether the write protect pin or the commands are controlling the sector protection.

Abstract: A semiconductor non-volatile memory device, particularly a flash memory array, having a chip configuration with a plurality of pins including a write protect pin, a serial in pin and an optional parallel data bus with input-output pins (I/O7-0), plus other pins, all electrically communicating with the memory array and particularly a sector protection register of variable size and location. The sector protection register defines which sectors or group of sub-sectors to protect and is controlled by the use of commands via the serial in pin or the optional input-output pins. The sector protection may be selectably controlled by either use of a signal to the write protect pin or use of commands via the serial in pin or the optional input-output pins to the command and control logic. A logic circuit instantly determines whether the write protect pin or the commands are controlling the sector protection.

Abstract: A semiconductor non-volatile memory device, particularly a flash memory array, having a chip configuration with a plurality of pins including a write protect pin, a serial in pin and an optional parallel data bus with input-output pins (I/O7-0), plus other pins, all electrically communicating with the memory array and particularly a sector protection register of variable size and location. The sector protection register defines which sectors or group of sub-sectors to protect and is controlled by the use of commands via the serial in pin or the optional input-output pins. The sector protection may be selectably controlled by either use of a signal to the write protect pin or use of commands via the serial in pin or the optional input-output pins to the command and control logic. A logic circuit instantly determines whether the write protect pin or the commands are controlling the sector protection.