Patents by Inventor Richard Dischler
Richard Dischler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230320021Abstract: Embodiments may relate an electronic device that includes a first server blade and a second server blade coupled with a chassis. The first and second server blades may include respective microelectronic packages. The electronic device may further include a waveguide coupled to the first and second server blades such that their respective microelectronic packages are communicatively coupled by the waveguide. Other embodiments may be described or claimed.Type: ApplicationFiled: June 8, 2023Publication date: October 5, 2023Applicant: Intel CorporationInventors: Telesphor Kamgaing, Johanna M. Swan, Georgios Dogiamis, Henning Braunisch, Adel A. Elsherbini, Aleksandar Aleksov, Richard Dischler
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Patent number: 11716826Abstract: Embodiments may relate an electronic device that includes a first platform and a second platform coupled with a chassis. The platforms may include respective microelectronic packages. The electronic device may further include a waveguide coupled to the first platform and the second platform such that their respective microelectronic packages are communicatively coupled by the waveguide. Other embodiments may be described or claimed.Type: GrantFiled: May 2, 2019Date of Patent: August 1, 2023Assignee: Intel CorporationInventors: Telesphor Kamgaing, Johanna M. Swan, Georgios Dogiamis, Henning Braunisch, Adel A. Elsherbini, Aleksandar Aleksov, Richard Dischler
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Patent number: 11656662Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.Type: GrantFiled: February 11, 2021Date of Patent: May 23, 2023Assignee: Intel CorporationInventors: Simon C. Steely, Jr., Richard Dischler, David Bach, Olivier Franza, William J. Butera, Christian Karl, Benjamin Keen, Brian Leung
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Patent number: 11581272Abstract: Embodiments may relate to a multi-chip microelectronic package that includes a first die and a second die coupled to a package substrate. The first and second dies may have respective radiative elements that are communicatively coupled with one another such that they may communicate via an electromagnetic signal with a frequency at or above approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.Type: GrantFiled: April 25, 2019Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Henning Braunisch, Adel A. Elsherbini, Georgios Dogiamis, Telesphor Kamgaing, Richard Dischler, Johanna M. Swan, Victor J. Prokoff
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Publication number: 20220196507Abstract: An apparatus is described. The apparatus includes a cover to enclose a junction between respective ends of first and second fluidic conduits. The first and second fluidic conduits transport a coolant fluid within an electronic system. The apparatus also includes a leak detection device to be located within a region that is enclosed by the cover when the junction is enclosed by the cover. The leak detection device is to detect a leak of the coolant fluid at the junction when the junction is enclosed by the cover. The first and second fluidic conduits extend outside the cover when the junction is enclosed by the cover. Another apparatus is also described. The other apparatus includes a leak detection device to detect a leak of coolant fluid from a specific component or junction in a liquid cooling system of an electronic system.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Inventors: Prabhakar SUBRAHMANYAM, Yi XIA, Ying-Feng PANG, Victor POLYANKO, Mark BIANCO, Bijoyraj SAHU, Minh T.D. LE, Carlos ALVIZO FLORES, Javier AVALOS GARCIA, Adriana LOPEZ INIGUEZ, Luz Karine SANDOVAL GRANADOS, Michael BERKTOLD, Damion SEARLS, Jin YANG, David SHIA, Samer MELHEM, Jeffrey Ryan CONNER, Hemant DESAI, John RAATZ, Richard DISCHLER, Bergen ANDERSON, Eric W. BUDDRIUS, Kenan ARIK, Barrett M. FANEUF, Lianchang DU, Yuehong FAN, Shengzhen ZHANG, Yuyang XIA, Jun ZHANG, Yuan Li, Catharina BIBER, Kristin L. WELDON, Brendan T. PAVELEK
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Patent number: 11108433Abstract: Embodiments herein may relate to an interconnect that includes a transceiver, wherein the transceiver is configured to generate a single side band (SSB) signal for communication over a waveguide and a waveguide interconnect to communicate the SSB signal over the waveguide. In an example, an SSB operator is configured to generate the SSB signal and the SSB signal can be generated by use of a finite-impulse response filter. Other embodiments may be described and/or claimed.Type: GrantFiled: November 30, 2018Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: Henning Braunisch, Georgios Dogiamis, Jeff C. Morriss, Hyung-Jin Lee, Richard Dischler, Ajay Balankutty, Telesphor Kamgaing, Said Rami
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Publication number: 20210255674Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: February 11, 2021Publication date: August 19, 2021Inventors: Simon C. Steely, JR., Richard Dischler, David Bach, Olivier Franza, William J. Butera, Christian Karl, Benjamin Keen, Brian Leung
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Patent number: 10963022Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.Type: GrantFiled: April 29, 2020Date of Patent: March 30, 2021Assignee: Intel CorporationInventors: Simon C. Steely, Jr., Richard Dischler, David Bach, Olivier Franza, William J. Butera, Christian Karl, Benjamin Keen, Brian Leung
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Publication number: 20200371566Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: April 29, 2020Publication date: November 26, 2020Inventors: Simon C. Steely, JR., Richard Dischler, David Bach, Olivier Franza, William J. Butera, Christian Karl, Benjamin Keen, Brian Leung
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Patent number: 10819445Abstract: Embodiments may relate to a transceiver chip. The transceiver chip may include a substrate that has a first transceiver component and a second transceiver component positioned therein. The transceiver chip may further include a well material that is positioned between the first transceiver component and the second transceiver component. The well material may mitigate cross-talk between the first transceiver component and the second transceiver component. Other embodiments may be described or claimed.Type: GrantFiled: November 20, 2018Date of Patent: October 27, 2020Assignee: Intel CorporationInventors: Telesphor Kamgaing, Georgios Dogiamis, Henning Braunisch, Hyung-Jin Lee, Richard Dischler
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Publication number: 20200315052Abstract: Embodiments may relate an electronic device that includes a first platform and a second platform coupled with a chassis. The platforms may include respective microelectronic packages. The electronic device may further include a waveguide coupled to the first platform and the second platform such that their respective microelectronic packages are communicatively coupled by the waveguide. Other embodiments may be described or claimed.Type: ApplicationFiled: May 2, 2019Publication date: October 1, 2020Applicant: Intel CorporationInventors: Telesphor Kamgaing, Johanna M. Swan, Georgios Dogiamis, Henning Braunisch, Adel A. Elsherbini, Aleksandar Aleksov, Richard Dischler
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Publication number: 20200303328Abstract: Embodiments may relate to a multi-chip microelectronic package that includes a first die and a second die coupled to a package substrate. The first and second dies may have respective radiative elements that are communicatively coupled with one another such that they may communicate via an electromagnetic signal with a frequency at or above approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.Type: ApplicationFiled: April 25, 2019Publication date: September 24, 2020Applicant: Intel CorporationInventors: Henning Braunisch, Adel A. Elsherbini, Georgios Dogiamis, Telesphor Kamgaing, Richard Dischler, Johanna M. Swan, Victor J. Prokoff
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Publication number: 20200273824Abstract: Embodiments may relate to a microelectronic package that includes a package substrate and a signal interconnect coupled with the face of the package substrate. The microelectronic package may further include a ground interconnect coupled with the face of the package substrate. The ground interconnect may at least partially surround the signal interconnect. Other embodiments may be described or claimed.Type: ApplicationFiled: March 29, 2019Publication date: August 27, 2020Applicant: Intel CorporationInventors: Telesphor Kamgaing, Georgios Dogiamis, Hyung-Jin Lee, Henning Braunisch, Richard Dischler
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Patent number: 10691182Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.Type: GrantFiled: May 20, 2019Date of Patent: June 23, 2020Assignee: Intel CorporationInventors: Simon C. Steely, Jr., Richard Dischler, David Bach, Olivier Franza, William J. Butera, Christian Karl, Benjamin Keen, Brian Leung
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Patent number: 10623106Abstract: Embodiments herein may relate to an interconnect that includes a transceiver, where the transceiver is configured to receive a data stream, convert the data stream to a quadrature amplitude modulation (QAM) mapping/shaping signal, where the QAM mapping/shaping signal is a frequency component of the data stream, convert the QAM mapping/shaping signal to a Hilbert transform signal, where the Hilbert transform signal includes a reverse order of an in-phase component of the QAM mapping/shaping signal and a reverse order of a quadrature component of the QAM mapping/shaping signal, convert the Hilbert transform signal to a QAM mapping/shaping signal, where the QAM mapping/shaping signal is a single sideband (SSB) time domain mm wave signal, where the SSB time domain mm wave signal is the Hilbert transform signal converted to a time domain signal, and communicate the SSB time domain mm wave signal over a waveguide using a waveguide interconnect.Type: GrantFiled: December 18, 2018Date of Patent: April 14, 2020Assignee: Intel CorporationInventors: Hyung-Jin Lee, Cho-ying Lu, Henning Braunisch, Telesphor Kamgaing, Georgios Dogiamis, Richard Dischler
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Publication number: 20190354146Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: May 20, 2019Publication date: November 21, 2019Inventors: Simon C. Steely, JR., Richard Dischler, David Bach, Olivier Franza, William J. Butera, Christian Karl, Benjamin Keen, Brian Leung
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Publication number: 20190149243Abstract: Embodiments herein may relate to an interconnect that includes a transceiver, where the transceiver is configured to receive a data stream, convert the data stream to a quadrature amplitude modulation (QAM) mapping/shaping signal, where the QAM mapping/shaping signal is a frequency component of the data stream, convert the QAM mapping/shaping signal to a Hilbert transform signal, where the Hilbert transform signal includes a reverse order of an in-phase component of the QAM mapping/shaping signal and a reverse order of a quadrature component of the QAM mapping/shaping signal, convert the Hilbert transform signal to a QAM mapping/shaping signal, where the QAM mapping/shaping signal is a single sideband (SSB) time domain mm wave signal, where the SSB time domain mm wave signal is the Hilbert transform signal converted to a time domain signal, and communicate the SSB time domain mm wave signal over a waveguide using a waveguide interconnect.Type: ApplicationFiled: December 18, 2018Publication date: May 16, 2019Applicant: Intel CorporationInventors: Hyung-Jin Lee, Cho-ying Lu, Henning Braunisch, Telesphor Kamgaing, Georgios Dogiamis, Richard Dischler
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Publication number: 20190115951Abstract: Embodiments herein may relate to an interconnect that includes a transceiver, wherein the transceiver is configured to generate a single side band (SSB) signal for communication over a waveguide and a waveguide interconnect to communicate the SSB signal over the waveguide. In an example, an SSB operator is configured to generate the SSB signal and the SSB signal can be generated by use of a finite-impulse response filter. Other embodiments may be described and/or claimed.Type: ApplicationFiled: November 30, 2018Publication date: April 18, 2019Applicant: Intel CorporationInventors: Henning Braunisch, Georgios Dogiamis, Jeff C. Morriss, Hyung-Jin Lee, Richard Dischler, Ajay Balankutty, Telesphor Kamgaing, Said Rami
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Publication number: 20190089409Abstract: Embodiments may relate to a transceiver chip. The transceiver chip may include a substrate that has a first transceiver component and a second transceiver component positioned therein. The transceiver chip may further include a well material that is positioned between the first transceiver component and the second transceiver component. The well material may mitigate cross-talk between the first transceiver component and the second transceiver component. Other embodiments may be described or claimed.Type: ApplicationFiled: November 20, 2018Publication date: March 21, 2019Applicant: Intel CorporationInventors: Telesphor Kamgaing, Georgios Dogiamis, Henning Braunisch, Hyung-Jin Lee, Richard Dischler