Abstract: A clock generation apparatus includes a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus, a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal, a flipflop and a comparator configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flipflop has an output that changes signaling state in response to an edge in the decision signal. The counter is reset when the decision signal is driven to the first signaling state.

Abstract: A method for managing a plurality of imaging devices in a vehicle includes determining that a change of data security mode is indicated for frames of image data transmitted over a first data communication link, determining whether a sensor management system has sufficient processing capacity to support the change of data security mode, increasing the processing capacity of the sensor management system by modifying data security settings for at least one other data communication link when the processing capacity of the sensor management system is insufficient to support the change of data security mode, and initiating the change of data security mode when the sensor management system has sufficient processing capacity to support the change of data security mode. The change of data security mode may include a change from an application-based to a link-based data security mode or a change from the link-based to the application-based data security mode.

Abstract: A receiving circuit has a clock generator circuit, a synchronization circuit and a controller. The clock generator circuit is configured to generate a base clock signal with a base frequency. The synchronization circuit is configured to synchronize edges in the base clock signal with edges in a Manchester-encoded data signal received over a serial bus. The controller is configured to detect that a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of sequence start condition that indicates a first type of transaction during which the Manchester-encoded data signal is received over the serial bus; configure a first timer to expire after a first timeout period; and ignore the first pulse when signaling consistent with the first type of sequence start condition has not been received before the first timer expires.

Abstract: A clock generation apparatus includes a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus, a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal, a flipflop and a comparator configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flipflop has an output that changes signaling state in response to an edge in the decision signal. The counter is reset when the decision signal is driven to the first signaling state.

Abstract: A receiving device, comprising: a clock generator circuit configured to generate a base clock signal; a counter configured to count cycles or edges of the base clock signal while a measurement pulse is received over a one-wire serial bus during a first transaction conducted over the one-wire serial bus, the measurement pulse having a pulse duration defined by a number of clock cycles of a transmitter clock signal; and a controller configured to adjust a count value of the counter when the counter is timing actuation of a trigger using a correction value that represents a difference between the cycles or edges of the base clock signal counted while the measurement pulse was being received and the number of clock cycles of the transmitter clock signal that defines the pulse duration.

Abstract: A data communication apparatus comprises a line driver configured to couple the data communication apparatus to a 1-wire serial bus; and a controller configured to: transmit a plurality of synchronization pulses over the 1-wire serial bus after a sequence start condition (SSC) has been transmitted over the 1-wire serial bus, the plurality of synchronization pulses being configured to synchronize one or more receiving devices coupled to the 1-wire serial bus to an untransmitted transmit clock signal; initiate an interrupt handling procedure when the plurality of synchronization pulses is encoded with a first value; and initiate a read transaction or a write transaction with at least one of the one or more receiving devices coupled to the 1-wire serial bus when the plurality of synchronization pulses is encoded with a second value.

Abstract: A data communication apparatus coupled to a serial bus has a protocol controller that configures a first plurality of subordinate devices with device identifiers unique within the first plurality of subordinate devices and configures a second plurality of subordinate devices with device identifiers unique within the second plurality of subordinate devices. A sequence start condition transmitted over the serial bus indicates either a first communication mode in which a clock signal is provided to the serial bus or a second communication mode in which no clock signal is provided. A device identifier associated with the first plurality of subordinate devices is used to transmit a first datagram over the serial bus in the first communication mode, and a device identifier associated with the second plurality of subordinate devices is used to transmit a second datagram over the serial bus in the second communication mode.

Abstract: A processing circuit is coupled to imaging devices through multiple data communication links. Each data communication link couples at least one imaging device with the processing circuit. The processing circuit is configured to determine when a change is required in a first data protection configuration that protects first image data transmitted over a first data communication link, and determine a second data protection configuration to be used when second image data is transmitted from a first imaging device over the first data communication link to an image processing circuit. The first data protection configuration or the second data protection configuration provides a partial integrity mode of data protection for frames of image data transmitted over the first data communication link. The partial integrity mode protects some, but not all frames of image data transmitted over the first data communication link using a message authentication code.

Abstract: A method for managing a plurality of imaging devices in a vehicle includes determining that a change of data security mode is indicated for frames of image data transmitted over a first data communication link, determining whether a sensor management system has sufficient processing capacity to support the change of data security mode, increasing the processing capacity of the sensor management system by modifying data security settings for at least one other data communication link when the processing capacity of the sensor management system is insufficient to support the change of data security mode, and initiating the change of data security mode when the sensor management system has sufficient processing capacity to support the change of data security mode. The change of data security mode may include a change from an application-based to a link-based data security mode or a change from the link-based to the application-based data security mode.

Abstract: A receiving circuit has a clock generator circuit, a synchronization circuit and a controller. The clock generator circuit is configured to generate a base clock signal with a base frequency. The synchronization circuit is configured to synchronize edges in the base clock signal with edges in a Manchester-encoded data signal received over a serial bus. The controller is configured to detect that a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of sequence start condition that indicates a first type of transaction during which the Manchester-encoded data signal is received over the serial bus; configure a first timer to expire after a first timeout period; and ignore the first pulse when signaling consistent with the first type of sequence start condition has not been received before the first timer expires.

Abstract: A subordinate device participates in address assignment through iterative communication with a host device. The subordinate device receives a first broadcast command over a multidrop serial bus, decouples a daisy chain input of the subordinate device from a daisy chain output of the subordinate device, receives a second broadcast command over the multidrop serial bus, responds to the second broadcast command when a signal received through the daisy chain input is in an active state, ignores the second broadcast command when the signal received through the daisy chain input is in an inactive state, and ignores subsequent broadcast commands after responding to the second broadcast command. Responding to the second broadcast command includes configuring a unique device identifier of the subordinate device using an address provided in the second broadcast command, and coupling the daisy chain input of the subordinate device to the daisy chain output of the subordinate device.

Abstract: A data communication apparatus coupled to a serial bus has a protocol controller that configures a first plurality of subordinate devices with device identifiers unique within the first plurality of subordinate devices and configures a second plurality of subordinate devices with device identifiers unique within the second plurality of subordinate devices. A sequence start condition transmitted over the serial bus indicates either a first communication mode in which a clock signal is provided to the serial bus or a second communication mode in which no clock signal is provided. A device identifier associated with the first plurality of subordinate devices is used to transmit a first datagram over the serial bus in the first communication mode, and a device identifier associated with the second plurality of subordinate devices is used to transmit a second datagram over the serial bus in the second communication mode.

Abstract: A data communication apparatus comprises a line driver configured to couple the data communication apparatus to a 1-wire serial bus; and a controller configured to: transmit a plurality of synchronization pulses over the 1-wire serial bus after a sequence start condition (SSC) has been transmitted over the 1-wire serial bus, the plurality of synchronization pulses being configured to synchronize one or more receiving devices coupled to the 1-wire serial bus to an untransmitted transmit clock signal; initiate an interrupt handling procedure when the plurality of synchronization pulses is encoded with a first value; and initiate a read transaction or a write transaction with at least one of the one or more receiving devices coupled to the 1-wire serial bus when the plurality of synchronization pulses is encoded with a second value.

Abstract: Systems and methods for variable stride counting for timed-triggers in a radio frequency front end (RFFE) bus modify how a master clock controls counters in slaves. In particular, instead of having the master clock change a counter at a slave device on a one-to-one clock tick-to-counter change, exemplary aspects of the present disclosure contemplate allowing a bus ownership master (BOM) to select a stride size wherein each clock tick causes the counter to change by the size of the stride. Clock ticks are then sent less frequently over the clock line of the RFFE bus. In this fashion, fewer clock ticks are required to change the counter to the trigger event.

Abstract: A multi-port data communication apparatus includes a first port having a first physical interface circuit configured to couple the multi-port data communication apparatus to a first serial bus that has a first line and a second line, a second port having a second physical interface circuit configured to couple the multi-port data communication apparatus to a second serial bus that has a first line and a second line, and a controller. The controller is configured to use the first port during a first transaction restricted to transmissions over the first serial bus and use the first port and the second port in a second transaction in which data is transmitted over the second line of the first serial bus and the second line of the second serial bus in accordance with timing provided by a clock signal transmitted over the first line of the first serial bus.

Abstract: A receive clock generated at a receiver coupled to a one-wire bus is synchronized in each clock cycle, permitting reception of a data frame of unlimited length without clock overrun or underrun. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in an output of the clock gating circuit. The clock gating circuit is disabled when an output of the counter indicates a preconfigured maximum count value. An edge synchronization circuit that synchronizes edges in the base clock signal with edges in a data signal received over the one-wire bus ignores edges in the data signal while the counter output has a value that is less than the maximum count value, and resets the counter in response to an edge detected in the data signal received over the one-wire bus.

Abstract: Sideband signaling in Universal Serial Bus (USB) Type-C communication link allows multiple protocols that are tunneled through a USB link, where sideband signals may be provided through the sideband use (SBU) pins. Further, the SBU pins may be transitioned between different modes of sideband signals. In particular, signals in an initial mode may indicate a need or desire transition to a second mode. After a negotiation, linked devices agree to transition, the two devices may transition to the second mode. By providing this inband sideband signaling that allows mode changes, more protocols can be tunneled with accompanying sideband signaling and flexibility of the USB link is expanded.

Abstract: An apparatus coupled to a single-wire serial bus through a line driver is configured to determine that a first sequence start condition (SSC) has been initiated when the single-wire serial bus transitions from first to second signaling states. The line driver drives the single-wire serial bus to the first signaling state after a first duration to complete the first SSC, and an arbitration window with plural timeslots is provided when the line driver presents a high impedance to the single-wire serial bus after the first SSC. The line driver drives the single-wire serial bus to the first signaling state in each timeslot of the plural timeslots in which the single-wire serial bus is driven to the second signaling state. After the arbitration window has expired, the apparatus transmits a second SSC and a Manchester encoded command addressed to at least one slave device.

Abstract: A receive clock generated at a receiver coupled to a one-wire bus is synchronized in each clock cycle, permitting reception of a data frame of unlimited length without clock overrun or underrun. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in an output of the clock gating circuit. The clock gating circuit is disabled when an output of the counter indicates a preconfigured maximum count value. An edge synchronization circuit that synchronizes edges in the base clock signal with edges in a data signal received over the one-wire bus ignores edges in the data signal while the counter output has a value that is less than the maximum count value, and resets the counter in response to an edge detected in the data signal received over the one-wire bus.

Abstract: Systems and methods for chip operation using serial peripheral interface (SPI) with reduced pin options contemplate eliminating the chip select pins, interrupt pins and/or reset pins for host (also referred to as master)-to-device (also referred to as slave) communication links, while preserving the possibility of backward compatibility for legacy devices if desired. The communication link may include a clock line, a host-to-device line, and a device-to-host line. The host may use specific sequences of signals on the clock and host-to-device line to provide start and stop sequence commands, interrupts, or reset commands. By consolidating these commands onto the clock and host-to-device line, pin count may be reduced for portions of the host and slave circuits. Likewise, fewer (or at least shorter potentially) conductive traces may be needed to interconnect the host to the device. Such changes may save cost, make layout design easier, and/or save space within a computing device.