Abstract: A plurality of integrated circuit chips (12) are packaged in a stack of chips in which a number of individual chip layers (10,120,130,132,134) are physically and electrically interconnected to one another and are peripherally sealed to one another to form an hermetically sealed package having a number of input/output pads (137a,139a,141a,156,158,160) on the surface of the upper (132) and lower (134) layers. Each chip layer comprises a chip carrier substrate having a chip cavity (22) on a bottom side and having a plurality of electrically conductive vias (40,42,44) extending completely around the chip cavity. Each substrate is formed with a peripheral sealing strip (46,48) on its top and bottom sides and mounts on its top side a chip that has its connecting pads (14) wire bonded to exposed traces (32,34) of a pattern of traces that are formed on the top side of the substrate and on intermediate layers (16,18,20) of this multi-layer substrate.

Abstract: A five stage background filter circuit 10 is disclosed which is capable of responding to background radiation changes at speeds which are from one to two orders of magnitude faster than conventional prior filters. The invention utilizes a cross scan multiplexing technique in combination with filter circuitry depicted in schematic overview in FIG. 1. Circuit 10 includes a differential amplifier 12, a sample and hold device 14, a responsivity corrector 16, a recursive filter 18, and a background subtractor 20. Output signals 11 from a focal plane array of detectors (shown in FIG. 3) are passed through impedance matching input resistors 12a,b to an amplifier. A sample and hold circuit 14a cyclically selects and stores a signal received from first stage 12. The detector outputs are then normalized by responsivity corrector stage 16 which employs a digital-to-analog converter 16a and random access memory 16c.