Patents by Inventor Richard E. Caddock, Jr.

Richard E. Caddock, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6253446
    Abstract: A fault current fusing resistor, comprising a substrate on which there is a line of resistive film formed of metal and glass in a conductive film, which line is closely confined by containing and sealing substances to prevent venting of vapor from the line during the fusing caused by an electrical fault condition.
    Type: Grant
    Filed: January 25, 1999
    Date of Patent: July 3, 2001
    Inventor: Richard E. Caddock, Jr.
  • Patent number: 5990780
    Abstract: A tight-tolerance, low-resistance, high-power chip resistor for mounting on a circuit board in parallel and adjacent relationship to such board. There are discrete terminal plates mounted on one surface of a substrate, in spaced-apart relationship to each other but still quite close to each other. Electrical connections are made by the customer to the terminal plates, at different regions thereof, without adversely affecting the tight-tolerance relationship. The terminal plates additionally provide heat spreading from the resistance film, enhancing the power handling capability of this low-resistance, high-power chip resistor.
    Type: Grant
    Filed: February 6, 1998
    Date of Patent: November 23, 1999
    Assignee: Caddock Electronics, Inc.
    Inventor: Richard E. Caddock, Jr.
  • Patent number: 5914648
    Abstract: A fault current fusing resistor, comprising a substrate on which there is a line of resistive film formed of metal and glass in a conductive film, which line is closely confined by containing and sealing substances to prevent venting of vapor from the line during the fusing caused by an electrical fault condition.
    Type: Grant
    Filed: February 12, 1996
    Date of Patent: June 22, 1999
    Assignee: Caddock Electronics, Inc.
    Inventor: Richard E. Caddock, Jr.
  • Patent number: 5621378
    Abstract: A power resistor having much improved heat dissipation ability to an underlying heatsink because a step or protuberance is provided that cooperates with the mounting bolt or screw to largely nullify the effects of molding-caused camber or curvature.
    Type: Grant
    Filed: April 20, 1995
    Date of Patent: April 15, 1997
    Assignee: Caddock Electronics, Inc.
    Inventors: Richard E. Caddock, Jr., Richard E. Caddock
  • Patent number: 5594407
    Abstract: A resistor combination and method, that is formed by a substrate having a resistive film on it, and pins extruding from one edge of the substrate and connected to the film. A U-shaped cold region is provided on the substrate around at least much of the film, and is so constructed that application of common high overload voltages to the pins causes vertical fracture of the substrate. The resulting substrate pieces are held by the pins to the circuit board. In one embodiment, a synthetic resin housing is provided around the substrate.
    Type: Grant
    Filed: July 12, 1994
    Date of Patent: January 14, 1997
    Assignee: Caddock Electronics, Inc.
    Inventor: Richard E. Caddock, Jr.
  • Patent number: 5481241
    Abstract: A low-cost heat sink-mounted power film resistor having a high power rating for its footprint size, and not incorporating any housing. The resistor is bolted or otherwise secured tightly to an external heat sink in high heat-conduction relationship, the external heat sink being contacted flatwise by a rectangular internal heat sink. The footprint size and shape of the internal heat sink correspond substantially to those of commercially-marketed power film resistors having molded synthetic resin housings. The internal heat sink is bonded in high heat-conductivity relationship to a ceramic chip having a resistive film on the side thereof remote from the heat sink. Over such resistive film is a thin environmental coating. The leads are provided and connected to spaced portions of the film, on metalization pads.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: January 2, 1996
    Assignee: Caddock Electronics, Inc.
    Inventor: Richard E. Caddock, Jr.
  • Patent number: 5481242
    Abstract: A telephone resistor combination and method, that is formed by a ceramic substrate having a resistive film on it, and pins on one edge of the substrate and connected to the film. A U-shaped cold region is provided on the substrate around at least much of the film, and is so constructed that application of common high overload voltages to the pins causes vertical fracture of the substrate. The resulting substrate pieces are held by the pins to the circuit board.
    Type: Grant
    Filed: May 10, 1994
    Date of Patent: January 2, 1996
    Assignee: Caddock Electronics, Inc.
    Inventor: Richard E. Caddock, Jr.
  • Patent number: 5361300
    Abstract: A balancing resistor and thermistor network for telephone circuits, and combination with an external relay, which reliably handles all three levels of adverse conditions, automatically resets under certain conditions, is physically small in size, and is strong. It is a flat ceramic substrate on both surfaces of which are screen-printed thick-film balancing resistor films. Also screen-printed on both surfaces are termination traces having portions so located that when the substrate substantially instantaneously fractures it reliably and substantially instantaneously breaks the circuits through the resistive films, the fracture occurring in response to a sudden high-voltage overload. Accordingly, there is no damage to, or melting or burning of, small wires in the telephone circuits at points near to or remote from the balancing resistor network. A thermistor film is screen-printed directly onto the substrate at a central region where there is no resistive film.
    Type: Grant
    Filed: March 26, 1993
    Date of Patent: November 1, 1994
    Assignee: Caddock Electronics, Inc.
    Inventor: Richard E. Caddock, Jr.
  • Patent number: 5304977
    Abstract: The film-type electrical power resistor includes a flat ceramic chip on the upper surface of which is screen-printed a resistive film. Terminals (leads) are mechanically and electrically connected to the upper chip surface, the terminals being such that the chip may be positioned by the terminals in a predetermined position in a mold cavity during manufacture of the resistor--prior to introduction of synthetic resin. The synthetic resin forms a molded electrically insulating body that embeds the portions of the terminals that are relatively near the chip, and also embeds the upper portion of the chip, but does not embed the bottom surface of the chip. The relationships are such that the lower chip surface may be engaged flatwise with a flat region of a chassis or heatsink. Accordingly, the chip is a substrate for the film, a heatsink for the film, an insulator maintaining the film electrically insulated from the chassis, and a spacer maintaining the terminals spaced from the chassis.
    Type: Grant
    Filed: April 6, 1992
    Date of Patent: April 19, 1994
    Assignee: Caddock Electronics, Inc.
    Inventor: Richard E. Caddock, Jr.
  • Patent number: 5254969
    Abstract: An apparatus and method by which a flat film-type resistor is intentionally caused to thermal-shock fracture in response to a predetermined high-voltage overload condition. A stressed spring wire is mounted on such film-type resistor and connected in circuit with it. A predetermined solder and temperature gradient are employed to hold the spring wire in bent condition until the solder melts, whereupon the spring flexes and the circuit breaks. Heatsink portions are provided in the circuit board for such resistor, and receive terminal pins thereof.
    Type: Grant
    Filed: March 12, 1993
    Date of Patent: October 19, 1993
    Assignee: Caddock Electronics, Inc.
    Inventor: Richard E. Caddock, Jr.
  • Patent number: 5231372
    Abstract: A method of making a compact high-voltage, high-power, thick-film screen-printed cylindrical resistor. A V-serpentine pattern is formed and adapted to fit on a cylindrical substrate having a diameter range of about 1/10 inch to about 1/2 inch. Such pattern is caused to have adjacent sections at a small acute angle to each other. Furthermore, the pattern is caused to have gaps at the open ends of the loops that are substantially wider than the gaps at the closed ends of the loops. In addition, the pattern is caused to have a sufficient number of undulations, and sufficient gap size, to achieve a predetermined voltage rating. Thereafter, the height of the pattern is changed to achieve a voltage coefficient substantially corresponding to the desired voltage coefficient. Furthermore, the resistive film material is altered to cause it to have a different resistivity, said latter resistivity being such that the same resistance value is achieved.
    Type: Grant
    Filed: October 9, 1991
    Date of Patent: July 27, 1993
    Assignee: Caddock Electronics, Inc.
    Inventor: Richard E. Caddock, Jr.
  • Patent number: 4766410
    Abstract: A high-voltage cylindrical film-type resistor has cup-shaped end caps that receive the ends of the cylindrical substrate, each end cap having a convexly-radiused rim that has a radius of at least 1.5 mils in a plane containing the substrate axis. In accordance with the method, the stated radius is achieved by abrading, preferably tumbling.
    Type: Grant
    Filed: October 14, 1986
    Date of Patent: August 23, 1988
    Assignee: Caddock Electronics, Inc.
    Inventor: Richard E. Caddock, Jr.
  • Patent number: 4132971
    Abstract: A highly stable noninductive film-type cylindrical resistor which can be economically mass-produced, with few rejects, even when the film is one having a very high resistance. This is accomplished by providing, in a silk-screened serpentine film pattern, parallel rows of bend or base regions which are on opposite sides of a longitudinal gap, and which are very wide in comparison to the remainder of the pattern. The exterior of the film is then lapped, until the resistance increases to a desired value, by effecting relative rotation between the resistor and a flexible lapping tape having a desired tension. For high-value resistors, the resistive film is caused to have a value (in ohms per square) higher than would be practical if the lapped bends were not relatively wide.
    Type: Grant
    Filed: February 28, 1977
    Date of Patent: January 2, 1979
    Inventor: Richard E. Caddock, Jr.