Abstract: A voltage supply circuit for an LCD driver employs two voltage dividers. A low current voltage divider includes resistive elements having a high resistance, thus providing a bias voltage with a low current. A high current voltage divider includes resistive elements having low resistances, thus providing a bias voltage with a high current. The high current voltage divider provides bias voltage levels with high current at the beginning of each time phase change. Thus, the liquid crystal display receives a high current when updating the bias voltage levels on the LCD, thereby producing a fast settling time. When the bias voltage levels are held constant, however, only the low current voltage divider provides the bias voltage levels to reduce power consumption. A halt mode prevents the liquid crystal display and driver from consuming any power by disconnecting both voltage dividers from the voltage source when in sleep mode.

Abstract: An electrostatic discharge (ESD) protection circuit for the output pads of an integrated circuit. The protection circuit includes an NMOS output transistor, an NMOS protection transistor and an NMOS bias transistor. The output and protection transistors are preferably embodied in a common merged transistor structure and have common drains connected to the output pad and common sources connected to the integrated circuit common. The bias transistor controls the gate-source bias of the protection circuit and operates to cause the output and the protection transistors to conduct current in proportion to the relative size of the transistors thereby maximizing the protection against damage by ESD.

Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.An input data register on the non-volatile memory die and a related multiplexer allows data from different sources to be loaded into the input data register depending on the mode of operation. Also, the output of the input data register is coupled to plural locations so that the destination of the data can also be switched responsive to the mode of operation.

Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. A plurality of feed-throughs are provided on the non-volatile memory die to provide communication paths from the processor die to package pads which are in the shadow of the non-volatile memory die relative to the processor die and thus prevent direct connection from the processor die to the package pad. In normal run mode, these pads are exclusively used as feed-through, providing a direct connection between a specific pad on the processor die and a specific pad on the package.

Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.The processor includes an in-system programming mode including first and second memory interface control registers on the processor die and the memory die, respectively, for receiving control bits from the processor core for controlling multiplexers on the dies. The various bit output lines of the first memory interface control register are coupled to the control inputs of the multiplexers.

Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.The processor can be programmed internally or externally. In the in-system programming mode, the processor program counter is used to fetch running instructions out of an on-board ROM instruction memory on the processor die. The processor core outputs an address into which data is to be programmed on its output data bus. The processor core then receives from an external device the data which is to be programmed into the selected address and outputs it serially onto the data bus and therefrom to the memory die.

Abstract: An integrated injection logic semiconductor structure having a double diffused lateral PNP transistor and an inverted vertical NPN transistor includes an extended region of epitaxial silicon doped N type by introduction of suitable impurity from two separate regions of the semiconductor surface. This extended N type region, which functions as the base of the PNP transistor, allows an adjoining P type region, which in prior art structures served only as the collector, to be utilized as both the collector and the collector contact, thereby reducing the size of the semiconductor structure. Said N type region substantially lessens the series resistance between the base of the NPN transistor and the collector of the PNP transistor, to thereby facilitate manufacture of integrated injection logic circuits operating faster, at higher current levels, and at higher gain than integrated injection logic circuits not utilizing this invention.

Abstract: A graduated multiple collector structure for inverted vertical bipolar transistors, integrated injection logic devices and the like. The invention increases the gain of more distant collectors toward which current flows laterally past intervening collectors from a base contact, and injector or the like. The series resistance drop and the current loss in the base-emitter junction are compensated for by progressively increasing the effective area of collectors further distant from the source of the base current. Although the graduated collector structure is applicable to a wide variety of semiconductor devices, it is particularly well suited for use in oxide-isolated integrated injection logic gates. A mathematical model is provided which can help to optimize designs incorporating the graduated collector structure.