Patents by Inventor Richard E. Downing

Richard E. Downing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Innovative dual-channel serial interface circuit scheme
    Patent number: 6192430
    Abstract: A mixed-signal processor (MSP) chip with a flexible serial interface which simultaneously accommodates two serial ports on a reduced number of pins. The pin definitions of these serial ports are configured to function well with several different external chips. Any two of these chips, or two of any one of these chips, may be used concurrently by the present MSP. When used with chips that require it, the present MSP chip provides a clock signal to each of these. When used with other chips, the MSP will can receive a clock signal from an external chip, and will then pass this signal through to any chip on the other of the two serial ports.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: February 20, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Ching-yuh Tsay, Richard E. Downing, George Paul Eaves, Craig Lance Dalley, Ian Lloyd Bower
  • Frame buffer, systems and methods
    Patent number: 5420609
    Abstract: A frame buffer is provided, including a plurality of input nodes and a plurality of multiplexing circuits. Each multiplexing circuit has a first input coupled to a respective input node. First control circuitry is provided for selectively coupling a second input of each multiplexer circuit to outputs of others of the multiplexing circuits. Second control circuitry is coupled to each multiplexing circuit for selecting between the first and second inputs.
    Type: Grant
    Filed: October 26, 1993
    Date of Patent: May 30, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Louis J. Izzi, Richard E. Downing
  • Frame buffer, method and circuit
    Patent number: 5414447
    Abstract: A frame buffer is provided, including a plurality of input nodes and a plurality of multiplexing circuits. Each multiplexing circuit has a first input coupled to a respective input node. First control circuitry is provided for selectively coupling a second input of each multiplexer circuit to outputs of others of the multiplexing circuits. Second control circuitry is coupled to each multiplexing circuit for selecting between the first and second inputs.
    Type: Grant
    Filed: October 26, 1993
    Date of Patent: May 9, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Louis J. Izzi, Richard E. Downing
  • Frame buffer, systems and methods
    Patent number: 5309173
    Abstract: A frame buffer is provided, including a plurality of input nodes and a plurality of multiplexing circuits. Each multiplexing circuit has a first input coupled to a respective input node. First control circuitry is provided for selectively coupling a second input of each multiplexer circuit to outputs of others of the multiplexing circuits. Second control circuitry is coupled to each multiplexing circuit for selecting between the first and second inputs.
    Type: Grant
    Filed: June 28, 1991
    Date of Patent: May 3, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Louis J. Izzi, Richard E. Downing