Abstract: An ideographic teletext transmission system based on the World System Teletext specification in which ideograms are displayed in the space of two character positions in each of three display rows, the ideogram code being defined by the corresponding bytes in one, e.g. the first, of the transmission packets corresponding to the three display rows and the corresponding bytes in another of the transmission packets corresponding to the three display rows being used to define an attribute code thereby affording a non-spacing attribute facility.

Abstract: A data display arrangement in which each of a number of different characters displayed on a CRT is defined by selected dots of a dot matrix. The stored character information from which character generating signals are produced is in the form of corresponding memory cell bit matrix. Such character information is read-out once in a number of successive scanning lines of each field to display the character normal height, and hitherto has been read-out twice in a number of successive pairs of scanning lines of each field to display the character double height. The invention provides a "double height algorithm" which modifies the read-out for double height character display such that part of a memory cell is read-out once and part is read-out twice. This results in a non-linear expansion of a double height character the effect of which is to maintain the visual baseline of a character row.

Abstract: A teletext decoder comprises a validation circuit for affording an output (V) when valid teletext data pulses are received. The validation circuit comprises an error checking circuit (SR, FCCC, MDCC, RACC) for affording outputs indicative of the number of errors existing in data pulses corresponding to a Framing Code, and Hamming protected magazine and row address data, and a validation check circuit (A, VCC) for affording an output V indicative of valid teletext data having been received when the combined total of said errors does not exceed one.

Abstract: A teletext decoder for teletext information comprising a plurality of different pages each of which is identified by a respective page number and each of which comprises a plurality of data packets each having a respective address. The teletext decoder includes a page memory and a pseudo page clearing arrangement in which a reference flag number (F) is allocated to a page header of a selected page. A packet related flag number (F) is allocated to each packet of the selected page as it is received. Utilisation of any data packet stored in the page memory, whose packet related flag number is not the same as the reference flag number is inhibited and the reference flag number for each successively selected page is changed.

Abstract: A teletext decoder is provided with a page memory having rows (R0 to R73) for storing corresponding packets of teletext data, the page memory being provided with at least one extra memory bit (F1, F2) for each row thereof, the extra memory bits constituting flags (F1, F2) which may be selectively set by the processor software in order to initiate selective action in respect of those packets which correspond to the flagged rows. The selective action might be to permit or prevent packets being written into memory or to alert the processor that immediate processing of a flagged packet is required.

Abstract: A teletext decoder arrangement has a page memory comprising a large number of chapters or portions in which individual pages can be stored. The arrangement has a plurality of data acquisition circuits which can acquire separate pages simultaneously. A register file is provided having a word location for each data acquisition circuit. A processor can load a memory chapter pointer byte into a word location when a page is to be acquired by the related data acquisition circuit so as to allot the memory chapter identified by the pointer byte for the storage of that page. In a practical embodiment four 4-bit word locations can have any one of 16 different 4-bit pointer bytes loaded into them to identify any one of 16 different memory chapters.

Abstract: A character display arrangement for displaying on a CRT rows of discrete characters. Digital codes represent both character data which identifies character shape and attribute data which identifies the attributes to be applied to displayed characters. The attribute data as received and stored in a display memory is in stack-coded form and relates to serial non-spacing attributes. The attribute and character data is read out from the memory one character row at a time. The character data is fed directly to a row buffer which has a position for each character position. The stack-coded attribute data is fed one group at a time to a pertaining fill register where it is decoded into explicit attribute data and fed to the row buffer to be associated with the character data.

Abstract: A teletext television receiver has a character memory comprising a common language set of characters and a plurality of sets of national option characters, each of which latter sets makes up a complete national language set when combined with the common language set. The totality of characters are arranged for addressing in two different modes. In one addressing mode, only one of the national option sets can be selected for page display as determined by control bits contained in the page header, so that the page can be only in one language. In the other addressing mode, all the national option sets can be selected for page display as determined by ghost row information of an acquired page, or locally by the receiver. This allows a display page to be in more than one language. FIGS. 3 and 4 show the code tables for the two addressing modes.

Abstract: Apparatus for addressing a character memory of a data display system in which displayed data is composed of discrete characters the shapes of which are determined by selected dots of a dot matrix. When character information conforms to different character modes of the form m.times.n.times.b, where m.times.n is a bit matrix format which is repeated b times to provide b-bits per displayed character dot, the stored character information includes mode bits which identify the mode. These mode bits are read out by logic control and addressing means by a first address and are used to determine a second address which varies according to the size of the mode and how many bit patterns it contains. The two addresses select all of the dot information required for the display of characters in real time.

Abstract: A data display arrangement in which selected characters arranged in rows of characters which are displayed on the screen of a CRT can be enlarged selectively at the expense of obscuring other characters, or of preventing other characters from being displayed enlarged size. The character size for a displayed character is determined by a size attribute code which accompanies the character code for the character. If an attribute code for a character is changed, the change in the size of the character as displayed can reveal previously obscured characters, which in turn may be displayed different size if an accompanying attribute code of that effect can now be implemented. These changes can result in ripple effects through the whole display.

Abstract: A character memory of a data display arrangement is divided into a plurality of separate memory sections which are available to provide characters for display only for respective sub-areas of a display screen. The invention is especially suited to providing high resolution character-based displays using so-called dynamically redefinable characters sets. A memory map MM containing the memory sections is addressed by a counter COU. A latch L2 initially sets the counter COU to the address of the first memory section. During each line scanning period a .div.2 divider DV is responsive to character column pulses CP to step the counter COU to address a new memory section address evey second character position. At the end of each line scanning period line pulses LP reset the counter COU to the first memory section address.

Abstract: A circuit arrangement for transmitting binary data elements `0` and `1` by frequency shift using two tone frequencies f0 and f1. The circuit arrangement comprises a modulator, an exclusive OR-gate and an integrator. A data signal DS produces from the modulator a digital signal DSS which by decoding of the integrator results in a tone signal TS comprising f0 or f1. The action of the OR-gate to which both signals DS and DSS are applied causes the amplitude of the tone signal TS to be substantially the same for each of the tone frequencies f0 and f1. The OR-gate may change either the effective resistive input into the integrator for each tone frequency or it may change the amplitude of the signal DSS for each tone frequency.

Abstract: In a television receiver adapted for the display of a normal television picture and/or message information in which both separated synchronizing signals and locally derived synchronizing signals are available, the selective use of one or the other of these two forms of synchronizing signals, having regard to different display circumstances, for the picture and message information display.

Abstract: A data pulse receiver arrangement is disclosed having a ringing circuit for establishing a clock pulse signal for data pulses which occur in a serial bit stream in a received information signal. The receiver arrangement is characterized in that comparator means are included for comparing the voltage across the ringing circuit with a reference voltage and for actuating a switching means for decoupling the input signal from the ringing circuit to prevent over-excitation thereof.