Abstract: A streaming programming mode may be implemented on user command in a phase change memory. In the streaming programming mode, accelerated programming may be achieved by ramping up to a voltage that it used for both reading and programming. Repeated programming operations may be streamed after one ramp up without ramping down the voltage on the memory cells between programming operations. This may save time. In addition, the memory may be read in between programming operations, again, without necessarily ramping down.

Abstract: A phase change memory includes a plurality of cells for storing data in the form of respective resistance levels, addressing circuits for addressing cells to be programmed, and the resistance levels are determined from comparison of cell currents of addressed cells with a reference current. A reference generator provides the sense amplifier with the reference current. The reference generator is provided with a reference select circuit to select the reference current from a plurality of verify currents based on program data to be stored in the cell.

Abstract: A partition may be made up of two planes of memory cells in a phase change memory. These planes may be configured so that they are not adjacent to one another. In some embodiments, this may mean that the adjacent planes may share sensing circuits, reducing the overall size of the memory array. In addition, by using non-adjacent planes to make up a partition, the planes may be spaced in a way which reduces resistance of power conveying lines. This may mean that smaller sized lines may be used, further reducing the size of the overall array.

Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.

Abstract: A phase change memory device includes a plurality of cells connected to bitlines and including respective phase change memory elements and cell select devices and an addressing circuit for selectively addressing at least one bitline and one cell connected thereto. A reading column bias circuit supplies a bitline voltage to the addressed bitline and cell. The bitline voltage includes the sum of a safe voltage and a reference select device voltage, wherein the reference voltage is equal to a select device voltage on the select device when a cell current flowing through the phase change memory element and the cell select device is equal to a safe current. The safe voltage and the safe current are such that phase transition of the phase change memory element is prevented in any bias condition including a cell voltage lower than the safe voltage and in any bias condition including the cell current lower than the safe current.

Abstract: A streaming programming mode may be implemented on user command in a phase change memory. In the streaming programming mode, accelerated programming may be achieved by ramping up to a voltage that it used for both reading and programming. Repeated programming operations may be streamed after one ramp up without ramping down the voltage on the memory cells between programming operations. This may save time. In addition, the memory may be read in between programming operations, again, without necessarily ramping down.

Abstract: A phase change memory includes a plurality of cells for storing data in the form of respective resistance levels, addressing circuits for addressing cells to be programmed, and the resistance levels are determined from comparison of cell currents of addressed cells with a reference current. A reference generator provides the sense amplifier with the reference current. The reference generator is provided with a reference select circuit to select the reference current from a plurality of verify currents based on program data to be stored in the cell.

Abstract: A self-referencing redundancy scheme in a content addressable memory may use a faulty bit table, populated during manufacturing, to indicate, not only the address of all the defective memory locations, but also the data which they should hold. Then, during read out, a read out state machine may access the faulty bit table, determine the data the faulty location should have held, and write that faulty data onto latches associated with the faulty memory elements.

Abstract: A multi-level cell memory that includes storing data in multiple cell densities is disclosed. The multi-level cell memory selectively includes error correction code. The multi-level cell memory may also include splitting cells into higher bits and lower bits in codewords.

Abstract: A multi-stage digital-to-analog converter has been presented. The multi-stage digital-to-analog converter may include a first digital-to-analog stage to output a first voltage and a second voltage in response to a first portion of a digital value, the first voltage being greater than the second voltage by a predetermined value, and a second digital-to-analog stage coupled to the first digital-to-analog stage to receive the first voltage and the second voltage and to generate a third voltage in between the first and the second voltages in response to a second portion of the digital value.

Abstract: A multi-stage digital-to-analog converter has been presented. The multi-stage digital-to-analog converter may include a first digital-to-analog stage to output a first voltage and a second voltage in response to a first portion of a digital value, the first voltage being greater than the second voltage by a predetermined value, and a second digital-to-analog stage coupled to the first digital-to-analog stage to receive the first voltage and the second voltage and to generate a third voltage in between the first and the second voltages in response to a second portion of the digital value.

Abstract: There exists a tradeoff between the fidelity of data storage and the number of bits stored in a memory cell. The number of bits may be increased per cell when fidelity is less important. The number of bits per cell may be decreased when fidelity is more important. A memory, in some embodiments, may change between storage modes on a cell by cell basis.

Abstract: A flash memory block erase operation permits multiple blocks to be erased simultaneously, even if the blocks are non-contiguous. A command sequence outputs multiple block addresses to the flash memory controller, which stores indicators of those addresses. When the command is completed, the flash memory initiates a block erase on all the specified blocks. The special command can be a multi-cycle bus command, made up of a sequence of single-cycle bus transfers using a standard format for the bus. The flash memory interface can contain the capability to interpret the command, retain the information transferred during the multiple bus cycles, and initiate the block erase operation after all the block addresses for that command have been received.

Abstract: There exists a tradeoff between the fidelity of data storage and the number of bits stored in a memory cell. The number of bits may be increased per cell when fidelity is less important. The number of bits per cell may be decreased when fidelity is more important. A memory, in some embodiments, may change between storage modes on a cell by cell basis.

Abstract: There exists a tradeoff between the fidelity of data storage and the number of bits stored in a memory cell. The number of bits may be increased per cell when fidelity is less important. The number of bits per cell may be decreased when fidelity is more important. A memory, in some embodiments, may change between storage modes on a cell by cell basis.

Abstract: A multi-level cell memory may include at least two status bits. The status bits may be examined to determine whether or not a write operation was successful after a power loss occurs.

Abstract: A data unit may be organized in error correcting rows and columns. Different error correcting algorithms may be utilized on the rows and columns. As a result, once a double error is identified in a given row, the location of each of the errors along the row may be determined using the column-wise error correcting algorithm. As a result, a single double error may be located and corrected after any other single errors have been corrected. In some embodiments, this may greatly increase the rate of successful error correction.

Abstract: There exists a tradeoff between the fidelity of data storage and the number of bits stored in a memory cell. The number of bits may be increased per cell when fidelity is less important. The number of bits per cell may be decreased when fidelity is more important. A memory, in some embodiments, may change between storage modes on a cell by cell basis.

Abstract: An Address Transition Detection (ATD) circuit for use in memory devices. The ATD circuit includes a pulse generator for generating an ATD pulse. For asynchronous memory device, the pulse generator generates the ATD pulse in response to an address transition, wherein for synchronous devices, the pulse generator generates the ATD pulse in response to control signals that indicate a valid address. The ATD circuit also includes a control circuit and a mask circuit. The control circuit is operative to asserting a first control signal in response to receiving the pulse. The mask circuit is coupled between the output of the pulse generator and the control circuit for preventing propagation of the ATD pulse if the first control signal is active.