Patents by Inventor Richard E. Kessler

Richard E. Kessler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10732684
    Abstract: According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: August 4, 2020
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: David A. Carlson, Richard E. Kessler
  • Patent number: 10721172
    Abstract: In an embodiment, a method includes, in response to detecting available memory of a destination node of a packet flow of nodes to the destination node being below a particular threshold, marking the destination node as being in a backpressure state. The destination node, in the backpressure state, sends a signal indicating a condition of packet backpressure to the nodes of the packet flow, and initiates a timer for a particular time period. The method further marks, at the end of the particular time period, the destination node as being in a bad actor state if the available memory is below the particular threshold, and as being in a good actor state if the memory is above the particular threshold. The method, in response to marking the destination node as being in a bad actor state, sends a signal to the nodes causing the nodes to drop packets directed to the destination node.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: July 21, 2020
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Richard E. Kessler, Nick Jamba, Victor Hart
  • Publication number: 20200183844
    Abstract: A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.
    Type: Application
    Filed: February 11, 2020
    Publication date: June 11, 2020
    Inventors: Richard E. KESSLER, David ASHER, Shubhendu S. MUKHERJEE, Wilson P. SNYDER, II, David CARLSON, Jason ZEBCHUK, Isam AKKAWI
  • Publication number: 20200097681
    Abstract: An encryption interface provides secure, low-latency communications between processors. A first processor block transforms initial data into encrypted data using a cipher for receipt by a second processor block, which transforms the encrypted data into decrypted data. The first processor block utilized a crypto circuit having a plurality of stages, each of which generate a subset of a cipher digit stream for encrypting the data. The second processor block receives and decrypts the encrypted data using a respective decryption circuit.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Georgios Angelopoulos, Steven C. Barner, Richard E. Kessler
  • Publication number: 20200099670
    Abstract: A network processor provides for in-line encryption and decryption of received and transmitted packets. For packet transmittal, a processor core generates packet data for encryption and forwards an encryption instruction to a cryptographic unit. The cryptographic unit generates an encrypted packet, and enqueues a send descriptor to a network interface controller, which, in turn, constructs and transmits an outgoing packet. For received encrypted packets, the network interface controller communicates with the cryptographic unit to decrypt the packet prior to enqueuing work to the processor core, thereby providing the processor core with a decrypted packet.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Richard E. Kessler, Shahe H. Krakirian
  • Publication number: 20200099669
    Abstract: A network processor provides for in-line encryption and decryption of received and transmitted packets. For packet transmittal, a processor core generates packet data for encryption and forwards an encryption instruction to a cryptographic unit. The cryptographic unit generates an encrypted packet, and enqueues a send descriptor to a network interface controller, which, in turn, constructs and transmits an outgoing packet. For received encrypted packets, the network interface controller communicates with the cryptographic unit to decrypt the packet prior to enqueuing work to the processor core, thereby providing the processor core with a decrypted packet.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventor: Richard E. Kessler
  • Patent number: 10592459
    Abstract: According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share resources, such as I/O devices. According to at least one example embodiment, a method of synchronizing access to an input/output (I/O) device in the multi-chip system comprises initiating, by a first agent of the multi-chip system, a first operation for accessing the I/O device, the first operation is queued, prior to execution by the I/O device, in a queue. Once the first operation is queued, an indication of such queuing is provided. Upon detecting, by a second agent of the multi-chip system, the indication of queuing the first operation in the queue, initiating a second operation to access the I/O device, the second operation is queued subsequent to the first operation in the queue.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: March 17, 2020
    Assignee: Cavium, LLC
    Inventor: Richard E. Kessler
  • Patent number: 10558573
    Abstract: A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: February 11, 2020
    Assignee: Cavium, LLC
    Inventors: Richard E. Kessler, David Asher, Shubhendu S. Mukherjee, Wilson P. Snyder, II, David Carlson, Jason Zebchuk, Isam Akkawi
  • Publication number: 20200014629
    Abstract: In an embodiment, a method includes, in response to detecting available memory of a destination node of a packet flow of nodes to the destination node being below a particular threshold, marking the destination node as being in a backpressure state. The destination node, in the backpressure state, sends a signal indicating a condition of packet backpressure to the nodes of the packet flow, and initiates a timer for a particular time period. The method further marks, at the end of the particular time period, the destination node as being in a bad actor state if the available memory is below the particular threshold, and as being in a good actor state if the memory is above the particular threshold. The method, in response to marking the destination node as being in a bad actor state, sends a signal to the nodes causing the nodes to drop packets directed to the destination node.
    Type: Application
    Filed: July 6, 2018
    Publication date: January 9, 2020
    Inventors: Richard E. Kessler, Nick Jamba, Victor Hart
  • Publication number: 20190107874
    Abstract: According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 11, 2019
    Inventors: David A. Carlson, Richard E. Kessler
  • Patent number: 10235211
    Abstract: A processor device comprises a plurality of virtual systems on chip, configured to utilize resources of a plurality of resources in accordance with a resource alignment between the plurality of virtual systems on chip and the plurality of resources. The processor device may further comprises a resource aligning unit configured to modify the resource alignment, dynamically, responsive to at least one event. Modifying the resource alignment, dynamically, may prevent a loss in throughput otherwise effectuated by the at least one event.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: March 19, 2019
    Assignee: Cavium, LLC
    Inventors: Rajan Goyal, Muhammad Raghib Hussain, Richard E. Kessler
  • Patent number: 10169080
    Abstract: According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share hardware resources. According to at least one example embodiment, a method of processing work item in the multi-chip system comprises designating, by a work source component associated with a chip device, referred to as the source chip device, of the multiple chip devices, a work item to a scheduler for scheduling. The scheduler then assigns the work item to another chip device, referred to as the destination chip device, of the multiple chip devices for processing, the scheduler is one of one or more schedulers each associated with a corresponding chip device of the multiple chip devices.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: January 1, 2019
    Assignee: Cavium, LLC
    Inventors: Richard E. Kessler, Wilson P. Snyder, II
  • Patent number: 10152102
    Abstract: According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: December 11, 2018
    Assignee: Cavium, LLC
    Inventors: David A. Carlson, Richard E. Kessler
  • Patent number: 10042778
    Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: August 7, 2018
    Assignee: Cavium, Inc.
    Inventors: Shubhendu S. Mukherjee, Bryan W. Chin, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler, Christopher Mikulis
  • Patent number: 10013385
    Abstract: A data processor includes an input/output bridge that provides enforcement of a security status on transactions between devices across the bridge. The bridge includes circuitry to parse a received request to obtain one or more identifiers, and compare the identifiers against one or more programmable lookup tables. Based on this comparison, the bridge can determine the security status of the transaction, as well as selectively forward the transaction based on the security status.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: July 3, 2018
    Assignee: Cavium, Inc.
    Inventors: Robert A. Sanzone, Wilson P. Snyder, II, Richard E. Kessler
  • Patent number: 10002099
    Abstract: An arbiter circuit manages and enforces arbitration and quality of service (QOS) among multiple devices accessing a resource, such as a memory. The arbiter circuit receives requests from a number of devices to use resources of a bridge connecting to a memory, and maintains a count of bridge resources available on a per-device and per-bus basis. The arbiter circuit operates to select a next one of the requests to grant a bridge resource based on the device originating the request, a count of the per-device resources available, and a count of the resources available to the bus connecting the device to the bridge.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: June 19, 2018
    Assignee: Cavium, Inc.
    Inventors: Robert A. Sanzone, Wilson P. Snyder, II, Richard E. Kessler
  • Patent number: 9906468
    Abstract: A network processor controls packet traffic in a network by maintaining a count of pending packets. In the network processor, a pipe identifier (ID) is assigned to each of a number of paths connecting a packet output to respective network interfaces receiving those packets. A corresponding pipe ID is attached to each packet as it is transmitted. A counter employs the pipe ID to maintain a count of packets to be transmitted by a network interface. As a result, the network processor manages traffic on a per-pipe ID basis to ensure that traffic thresholds are not exceeded.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: February 27, 2018
    Assignee: Cavium, Inc.
    Inventors: Richard E. Kessler, Michael Sean Bertone
  • Patent number: 9858222
    Abstract: A circuit manages and controls access requests to a register, such as a control and status register (CSR) among a number of devices. In particular, the circuit selectively forwards or suspends off-chip access requests and forwards on-chip access requests independent of the status of off-chip requests. The circuit receives access requests at a plurality of buses, one or more of which can be dedicated to exclusively on-chip requests and/or exclusively off-chip requests. Based on the completion status of previous off-chip access requests, further off-chip access requests are selectively forwarded or suspended, while on-chip access request are sent independently of off-chip request status.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: January 2, 2018
    Assignee: Cavium, Inc.
    Inventors: Robert A. Sanzone, Wilson P. Snyder, II, Richard E. Kessler
  • Publication number: 20170308408
    Abstract: A processor device comprises a plurality of virtual systems on chip, configured to utilize resources of a plurality of resources in accordance with a resource alignment between the plurality of virtual systems on chip and the plurality of resources. The processor device may further comprises a resource aligning unit configured to modify the resource alignment, dynamically, responsive to at least one event. Modifying the resource alignment, dynamically, may prevent a loss in throughput otherwise effectuated by the at least one event.
    Type: Application
    Filed: April 22, 2016
    Publication date: October 26, 2017
    Inventors: Rajan Goyal, Muhammad Raghib Hussain, Richard E. Kessler
  • Publication number: 20170228007
    Abstract: According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.
    Type: Application
    Filed: April 27, 2017
    Publication date: August 10, 2017
    Inventors: David A. Carlson, Richard E. Kessler