Abstract: In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.

Abstract: An embodiment of the present invention is method of forming an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit lines being connected in a hierarchical bit line structure, comprising at least one local bit line pair and one global bit line pair, a sensing circuit connected to the global bit line pair detects a differential voltage transition on either line during a read access and provides a sensing strobe signal.

Abstract: In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.

Abstract: An embodiment of the present invention is an SRAM memory array comprising memory cells with each cell containing seven devices, wherein the basic storage nodes, which store the true and complement of the data, are constructed from six devices, forming a cross-coupled flip-flop cell. One internal storage node of this cell being connected to a separate read-pass device which passes the state of this node to a local bit line (LBL) for single-ended sensing, with the gate of this separate read-pass device connected to a separate read-word line.

Abstract: An embodiment of the present invention is an SRAM memory array comprising memory cells with each cell containing six devices, the storage nodes which store the true and complement of the data are constructed from a four device, cross coupled flip-flop cell, wherein one internal storage node of this cell is connected through an access pass gate to one local bit line (LBL), the second internal storage node connected in a like manner to a second LBL, each LBL connected to a limited number, e.g. 8 to 32 of other similar storage cells, the two LBLs each connected to the gate of a separate read head nFET for discharging to ground one of two previously precharged global read lines so as to pass the inverse of the signal on the LBL and thus on the read head gate to a global read/write bit line.

Abstract: An embodiment of the present invention is method of forming an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit lines being connected in a hierarchical bit line structure, comprising at least one local bit line pair and one global bit line pair, a sensing circuit connected to the global bit line pair detects a differential voltage transition on either line during a read access and provides a sensing strobe signal.

Abstract: An embodiment of the present invention is an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit lines being connected in a hierarchical bit line structure, comprising at least one local bit line pair and one global bit line pair, a sensing circuit connected to the global bit line pair detects a differential voltage transition on either line during a read access and provides a sensing strobe signal.

Abstract: In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.

Abstract: Systems and methods for a DRAM concurrent refresh engine with processor interface. In exemplary embodiments, memory cells requiring periodic refresh at least once each for a specified refresh interval and words of an array organized banks in which the banks are selected for access by a bank-enable signal, each bank having a word decoder accepting one of two refresh word addresses, one refresh word address for a normal access, and the other for a refresh access, one of the word addresses selected by two separate enable signals, provided by on-macro refresh logic, which includes instructions to select one bank for refresh when no normal access occurs and select one bank for refresh concurrently with a normal access having no bank conflicts, the refresh logic maintaining the refresh status, timing of the refresh interval, and insuring all memory cells are refreshed within the refresh interval.

Abstract: In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.

Abstract: An embodiment of the present invention is an SRAM memory array comprising memory cells with each cell containing six devices, the storage nodes which store the true and complement of the data are constructed from a four device, cross coupled flip-flop cell, wherein one internal storage node of this cell is connected through an access pass gate to one local bit line (LBL), the second internal storage node connected in a like manner to a second LBL, each LBL connected to a limited number, e.g. 8 to 32 of other similar storage cells, the two LBLs each connected to the gate of a separate read head nFET for discharging to ground one of two previously precharged global read lines so as to pass the inverse of the signal on the LBL and thus on the read head gate to a global read/write bit line.

Abstract: An embodiment of the present invention is an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit lines being connected in a hierarchical bit line structure, comprising at least one local bit line pair and one global bit line pair, a sensing circuit connected to the global bit line pair detects a differential voltage transition on either line during a read access and provides a sensing strobe signal.

Abstract: An embodiment of the present invention is an SRAM memory array comprising memory cells with each cell containing seven devices, wherein the basic storage nodes, which store the true and complement of the data, are constructed from six devices, forming a cross-coupled flip-flop cell. One internal storage node of this cell being connected to a separate read-pass device which passes the state of this node to a local bit line (LBL) for single-ended sensing, with the gate of this separate read-pass device connected to a separate read-word line.

Abstract: A hierarchical DRAM array, DRAM macro and logic chip including the DRAM macro embedded in the logic. DRAM array columns are segmented with a small number (e.g., 2-64) of cells connected to a local bit line (LBL) in each segment. Each LBL drives a sense device that drives a global read bit line (GRBL). When a cell storing a high is selected, the cell drives the LBL high, which turns the sense device on to drive the GRBL low. Segments may be used individually (as a macro) or combined with other segments sharing a common GRBL.

Abstract: Architectures, methods and systems are presented which combine a multiple of directories (e. g. L1 and L2 directory) into a single directory, while still allowing the individual levels to use their own organization which is best for overall performance. This integration is performed without compromising the organization at each level. With some small additions to the L2 directory, it is used simultaneously to perform both the L1 and L2 directory functions. Additionally, the same organizational structure allows the L2 array to serve both as a traditional L1 and simultaneous L2 array.

Abstract: An electronic computer memory system has first and second intermediate memory levels for use between a central processing unit and a main memory level. One or more buffer arrays have two sets of bus lines. A first set of buffer array bus lines communicates with associated bus lines of the first and second intermediate memory arrays. The second set of buffer array bus lines contains a number of bus lines less than the number of bus lines in the first memory array. By providing one or more buffers with two sets of bus lines, data can be transferred between the main memory level and the buffer or one intermediate memory level while data in the other intermediate memory level is operated on by a the central processing unit. By providing the buffer with one set of bus lines equal to the number of bus lines of the first and second intermediate memory arrays, high speed data transfer between the intermediate memory arrays can be achieved.

Abstract: A cache memory having rows of memory cells, each row having at least first and second blocks of memory cells. Each memory cell stores a data signal, has at least one word line input, and at least one bit line input/output. A word line connects the word line inputs of at least first, second, third, and fourth memory cells in a row of the cache memory. The first and third memory cells are contained in the first block, while the second and fourth memory cells are contained in the second block. First and second sense amplifiers or write drivers are provided for reading data from or writing data to memory cells. First and second switches having control inputs connect the bit line inputs/outputs of the first and second memory cells, respectively, to the first sense amplifier/write driver. Third and fourth switches having control inputs switchably connect the bit line inputs/outputs of the third and fourth memory cells, respectively, to the second sense amplifier/write driver.

Abstract: An on-chip VLSI cache architecture including a single-port, last-select, cache array organized as an n-way set-associative cache (having n congruence classes) including a plurality of functionally integrated units on-chip in addition to the cache array and including a normal read/write CPU access function which provides an architectural organization for allowing the chip to be used in (1) a fast, "late-select" operation which may be provided with any desired degree of set-associativity while achieving an effective one-cycle write operation, and (2) a cache reload function which provides a highly parallel store-back and reload operation to substantially reduce the reload time, particularly for a store-in cache organization.

Abstract: A general bit manipulator structure for parallel accessing a variable width data bus wherein, with a data bus of variable width N.sub.c and a data field of N.sub.f, the structure can place the data field on the data bus with bit 1 of the data field aligned with a selected bit n within the data bus width. If the data field N.sub.f extends beyond the end of the data bus, the overflow bits of the data field are "wrapped around" and placed at the beginning of the data bus starting at position 1 of the data bus. Also, special signals are generated and accompany these overflow or wrapped bits. Furthermore, select signals are generated to indicate which bits of the data bus contain valid data when the width of the data field is less than the width of the data bus. The structure includes a modulo N.sub.c combinational ring shifter for aligning the data field with the data bus.

Abstract: A display architecture is disclosed which supports a variable, selectable number of bits per chip and a variable, selectable segment width. The architecture comprises a plurality of dynamic memory chips and a function generator. Each of the memory chips includes at least two data islands wherein each data island has its own data in/out line, chip select and increment bit supplied by the function generator. The function generator receives a starting address X.sub.o, Y.sub.o, the data path width N.sub.D and an encoded segment width S. A bit incrementer in the function generator generates increment bits A.sub.I based on the externally supplied modulo N.sub.D. The function generator generates the physical word address w.sub.o and physical bit address b.sub.o based on the starting address X.sub.o, Y.sub.o, the data path width N.sub.D and the encoded segment width S. Logic circuitry is provided which is responsive to an overflow bit produced by the bit incrementer to control spill and wrap functions.