Abstract: A method and apparatus for determining integrated circuit layouts from a virtual circuit description and specification of a technology. Starting with high-level descriptions of a circuit, a virtual geometric description of the circuit is developed using a virtual grid described in terms of reference points relative to a substrate surface. The relationships among the reference points are expressed as fractions of variables that can also be used to define the design rules. When the technology is specified, the relationships among the reference points is determined, as in the layout of the integrated circuit.

Abstract: The process includes the steps of (1) forming a pattern of indentations and adjacent boundary ridges in a base layer of glass which is heated to a temperature where it is formable but not flowing, (2) depositing electrically conducting first connecting elements on the upper surface of the base glass layer, with each first connecting element extending from an indentation to a point on an adjacent ridge, (3) positioning a solar cell into each indentation in the base glass layer in such a manner that the lower surface of the solar cell comes in electrical contact with one end of a first connecting element, (4) depositing electrically conducting second connecting elements which extend between the end of the first connecting elements on a ridge to the top surface of a solar cell in an adjacent indentation, and (5) forming a top glass layer which is in intimate contact with the product of steps 1-4.

Abstract: The process comprises the following steps: (1) forming a glass sheet which defines a substrate layer for the solar cell product; (2) forming a diffusion barrier layer on at least one surface of the substrate; (3) forming a first electrically-conductive layer on the diffusion barrier, the first electrically-conductive layer being a first electrode in the solar cell product; (4) depositing small-grain polycrystalline silicon in a thin film, i.e., 10-100 micrometers, on the first electrode layer; (5) recrystallizing, typically by heating, the deposited polycrystalline silicon until it reforms into large-grain polycrystalline or single-crystal silicon; (6) forming a PN junction in the recrystallized silicon layer; and (7) forming a second electrically-conductive layer on the recrystallized silicon layer, the second electrically-conductive layer being a second electrode in the solar cell product.