Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N?1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

Abstract: A memory system includes a memory controller and a memory component coupled to each other. The memory controller includes an interface to receive a first signal and a second signal from the memory component, wherein the first signal comprises a first symbol and the second signal comprises a second symbol. A first circuit of the memory controller receives the first signal by sampling the first symbol using a first timing offset relative to a reference clock signal, and a second circuit of the memory controller receives the second signal by sampling the second symbol using a second timing offset relative to the reference clock signal. The first timing offset is independent of the second timing offset.

Abstract: A variable depth write data buffer is provided in a memory device coupled to a master device by an interconnect structure in an embodiment of the present invention. The variable depth write data buffer reduces a delay, or W-R turnaround bubble, time between a read operation and a write operation of a memory device memory core. The variable depth write buffer is programmable to store 1 to 4 data packets in an embodiment of the present invention. The variable depth write data buffer may also be programmed for multiple memory device configurations. A method preloads write data without address information into a write data buffer and a subsequent WRITE command causes the previously loaded write data to be retrieved from the write data buffer and written to a memory core according to an embodiment of the present invention.

Abstract: A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.

Abstract: A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The second plurality of signal lines carries first address information from the integrated circuit buffer device to the first memory device. A third plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The third plurality of signal lines carries first control information from the integrated circuit buffer device to the first memory device. A first signal line is coupled to the first memory device and the integrated circuit buffer device. The first signal line carries a first signal from the integrated circuit buffer device to the first memory device.

Abstract: A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage.

Abstract: A memory controller is disclosed. In one particular exemplary embodiment, the memory controller may comprise a first transmitter to output first and second write commands synchronously with respect to a clock signal, a second transmitter to output first data using a first timing offset such that the first data arrives at a first memory device in accordance with a predetermined timing relationship with respect to a first transition of the clock signal, and a third transmitter to output second data using a second timing offset such that the second data arrives at a second memory device in accordance with a predetermined timing relationship with respect to a second transition of the clock signal.

Abstract: A memory module having a termination component. The memory module includes multiple memory devices, a termination component, a control signal path and multiple data signal paths. The control signal path is coupled to each of the memory devices and the termination component, and extends along the memory devices such that signals propagating on the control signal path propagate past each of the memory devices in succession before reaching the termination component. A unique set of data signal paths is coupled to each of the memory devices.

Abstract: A memory controller comprises a circuit to convert a set of parallel constituent bits to a serial stream of constituent bits. A first output driver receives at least four bits of the serial stream of constituent bits in succession from the circuit. The first output driver outputs the at least four bits of the serial stream of constituent bits onto a first external signal line.

Abstract: A memory device having a clock multiplier circuit. The memory device includes a clock generating circuit to receive a first clock signal having a first frequency and to generate a second clock signal having a second frequency that is a multiple of the first frequency. The memory device includes a data receive circuit to receive data at the frequency of the second clock signal and may also include a data transmit circuit to transmit data at the frequency of the second clock signal. Further, the clock generating circuit may additionally generate a third clock signal having a third frequency that is also a multiple of the first frequency, the third clock signal being supplied to a control circuit of the memory device to time the reception of control and/or address signals therein. In a particular embodiment the second frequency is a four-times or eight-times multiple of the first frequency, and the third frequency is a two-times multiple of the first frequency.

Abstract: A method, system and memory controller that uses adjustable write data delay settings. The memory controller includes control transmit circuitry, data transmit circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data transmit circuitry transmits data signals to the memory devices via respective data signal paths. The timing circuitry delays transmission of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices.

Abstract: An integrated circuit buffer device comprises a first receiver circuit to receive control information and address information from a controller device. A first interface includes a first interface portion to provide a first address to a first memory device. A second interface portion provides a first control signal to the first memory device. The first control signal specifies a read operation such that the first memory device provides a first data, accessed from a memory location based on the first address, to the integrated circuit buffer device in response to the first control signal specifying the read operation. A third interface portion provides a first clock signal to the first memory device. The first clock signal synchronizes communication of the first control signal from the integrated circuit buffer device to the first memory device. A fourth interface portion receives the first data. A second interface includes a first interface portion to provide a second address to a second memory device.

Abstract: A memory module includes an integrated circuit buffer device that receives control information via a connector interface. A first plurality of signal lines carries a first address from the integrated circuit buffer device to a first memory device. A second plurality of signal lines carries a first control signal from the integrated circuit buffer device to the first memory device. The first control signal specifies a read operation by the first memory device such that the first memory device provides first data, accessed from a memory location in the first memory device based on the first address, to the integrated circuit buffer device. A first signal line carries a first signal from the integrated circuit buffer device to the first memory device. The first signal synchronizes communication of the first control signal from the integrated circuit buffer device to the first memory device. A third plurality of signal lines carries a second address from the integrated circuit device to the second memory device.

Abstract: A memory module having a termination component. The memory module includes first and second memory devices, a termination component and three sets of signal lines. A first set of signal lines is coupled to the first memory device and dedicated to data transfers involving the first memory device. A second signal lines is coupled to the second memory device and dedicated to data transfers involving the second memory device. A third set of signal lines is coupled to the first and second memory devices and the termination component such that a signal propagating on the third set of signal lines propagates past the first memory device before reaching the second memory device, and propagates past the second memory device before reaching the termination component.

Abstract: An integrated circuit buffer device comprising a receiver circuit to receive control information and address information. A first interface portion provides at least a first control signal that specifies a write operation to a first memory device. The first control signal corresponds to the control information. A second interface portion provides a first address to the first memory device. The first address corresponds to the address information. The first address specifies a memory location for the write operation to the first memory device. A third interface portion provides a first signal to the first memory device. The first signal synchronizes communication of the first control signal from the integrated circuit buffer device to the first memory device. A fourth interface portion provides at least a second control signal that specifies a write operation to a second memory device. The second control signal corresponds to the control information.

Abstract: A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment. The memory device includes an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.

Abstract: A method, system and memory controller that uses adjustable read data delay settings. The memory controller includes control transmit circuitry, data reception circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data reception circuitry receives data signals from the memory devices via respective data signal paths. The timing circuitry delays reception of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices.

Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.

Abstract: A method and apparatus provides a mask key that is used instead of mask data. In an embodiment of the present invention, a write mask key is generated by a memory controller and transferred to a memory device that uses the write mask key to determine whether to write a data value to a storage array. A plurality of decoders, an OR logic gate tree and a binary propagation tree is used to provide the write mask key that reduces latency while using the approximate same circuit area and allows for the use of standard software tools in an embodiment of the present invention. A plurality of log2 decoders is coupled to a plurality of OR logic gates in the OR logic gate tree.

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.