Abstract: A double buffered flash bank. In one embodiment, a flash interface may be programmed by a register interface with a first set of data while a second set of data is being written to the register interface. In one embodiment, flash banks may be programmed in parallel using latched register interfaces. For example, while data from a first register interface is being written to the first flash bank and data from a second register interface is being written to a second flash bank, new data may be written to the first register interface and to the second register interface. The new data may then be written from the first register interface to the first flash bank and from the second register interface to the second flash bank.

Abstract: A method and apparatus for hot-docking is disclosed. In one embodiment, a portable computer system includes a bus bridge and a bus coupled to the bus bridge. The bus may have one or more peripheral devices or peripheral interfaces coupled to it. The bus may also be coupled to a docking interface having a bus switch. The bus switch, when closed and the computer is coupled to a docking station, may couple the bus to a peripheral interface in a docking station. The bus switch may close responsive to docking, thereby completing the electrical coupling of the bus to the peripheral interface in the docking station. The closing of the bus switch may be controlled by the docking interface such that operations on the bus are not interrupted during the docking procedure.

Abstract: An interface that allows the host CPU and the keyboard controller in a PC to share a common BIOS ROM includes a logic circuit that receives a set of input signals and produces a set of signals that emulates a jump instruction op-code that causes the host CPU to vector to a specified address location in the system memory map normally reserved for the system ROM BIOS code, whenever both the host CPU and keyboard controller are contending for access to the BIOS ROM.

Abstract: A method and apparatus for providing power management functions in a computer or other electronic system which includes a primary power supply, a trickle power supply and a battery back-up power supply. A power management circuit includes a storage element which stores an indication of the current turn-on or turn-off condition of the primary power supply. The power management circuit also includes a group of logic gates which process signals which are supplied to the storage element under normal operating conditions to control the turn-on or turn-off condition of the primary power supply. The power management circuit senses when the trickle supply is deactivated due to a line power failure or the like, and subsequently switches the power supply inputs of the storage element and certain of the logic gates from the trickle supply to the battery back-up supply.

Abstract: A floppy disk data separator includes a phase lock loop which locks onto a clock signal that is synchronized to the data stream being read from the disk. The clock signal is derived from a sync counter which is reset each time a data bit is received from the disk. The output of the sync counter is an edge delayed by 1/4 of a bit time. The next edge of the clock occurs each 1/2 bit time after that until the next data bit is received. These clock signals are phase compared with clock signals produced in the phase lock loop to synchronize the clock to the disk data. In another aspect of the invention, the phase lock loop is operated in either a low-gain or high-gain mode.