Patents by Inventor Richard E. Wallace

Richard E. Wallace has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11972979
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts, mask layer partially filling a first channel over a first gate contact, and a fill metal filling a second channel over a second gate contact that is adjacent to the first gate contact.
    Type: Grant
    Filed: June 7, 2023
    Date of Patent: April 30, 2024
    Assignee: Intel Corporation
    Inventors: Leonard P. Guler, Michael Harper, Suzanne S. Rich, Charles H. Wallace, Curtis Ward, Richard E. Schenker, Paul Nyhus, Mohit K. Haran, Reken Patel, Swaminathan Sivakumar
  • Publication number: 20240096785
    Abstract: An IC device includes a transistor, a first layer, and a second layer. The first layer is coupled to the transistors and is between the transistor and the second layer in a first direction. The first layer includes a first structure and a second structure. The first structure includes a first metal (e.g., Ru). The second structure includes a second metal (e.g., Cu). The second structure may be wrapped around by a different material that may include a third metal (e.g., Co). The first structure may be shorter than the second structure in the first direction and narrower than the second structure in a second direction orthogonal to the first direction. The first structure may be closer to the second layer than the second structure in the first direction. The first structure may be a wordline of a memory. The second structure may be a bitline.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Applicant: Intel Corporation
    Inventors: June Choi, Charles Henry Wallace, Richard E. Schenker, Nikhil Jasvant Mehta
  • Publication number: 20240071917
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 29, 2024
    Inventors: Richard E. SCHENKER, Robert L. BRISTOL, Kevin L. LIN, Florian GSTREIN, James M. BLACKWELL, Marie KRYSAK, Manish CHANDHOK, Paul A. NYHUS, Charles H. WALLACE, Curtis W. WARD, Swaminathan SIVAKUMAR, Elliot N. TAN
  • Publication number: 20040093683
    Abstract: A device is disclosed for controlling the operation of a vacuum cleaning assembly, which assembly includes a vacuum-creating source, a vacuum hose attachable to the vacuum-creating source, a vacuum cleaning head, and a suction wand operatively connecting the vacuum hose to the cleaning head. The device includes a wand connection member having a housing with a first end attachable to the vacuum hose and a second end attachable to the suction wand. A valve element is disposed in the housing. The valve element is movable between a closed position to block the vacuum between the vacuum-creating source and the cleaning head, and an open position to provide full vacuum between the vacuum-creating source and the cleaning head. A transfer mechanism is secured to the housing for controlling the movement of the valve element between its closed and open positions.
    Type: Application
    Filed: November 15, 2002
    Publication date: May 20, 2004
    Inventor: Richard E. Wallace
  • Patent number: 4860284
    Abstract: Apparatus and method for identifying the location of a lost token signal continuously transmitted on transmission paths interconnecting nodes of a network to sequentially enable the nodes to write data onto the network. The arrival of the token signal at each node is recorded in counter states of a token track counter corresponding with the node. The recorded binary counter states are compared upon the failure of the token signal to arrive at a node to detect mismatches and transitions occurring between adjacent nodes counter states identifying the network location of the lost token signal.
    Type: Grant
    Filed: April 20, 1988
    Date of Patent: August 22, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: David B. Brown, Richard E. Wallace
  • Patent number: 4752924
    Abstract: A data communication network comprising a plurality of nodes interconnecting transmission paths in a ring structure arranged to propagate data messages between data systems coupled to the network by the nodes in opposite directions around the network ring structure. An executive node having ring interface units interconnecting ones of the transmission paths is arranged to selectively couple a network control processor with various sectors of the transmission paths to enable the network control processor to control the traffic flow of data messages on the data communication network.
    Type: Grant
    Filed: September 5, 1985
    Date of Patent: June 21, 1988
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Joseph W. Darnell, Allen D. Fergeson, David M. Rouse, Richard E. Wallace, Charles M. Zelms
  • Patent number: 4683563
    Abstract: A data communication network comprising ring transmission paths (0,1) interconnecting ring interface nodes (RI1, RI2, RI3) coupled with a node processor and data systems and arranged to propagate data messages along the ring transmission paths between the data systems. Each node is arranged to detect failure of the node to propagate a data message to another node and to flush the data communication network by force reading data messages off the ring transmission paths into the blocked node processor. A node is arranged to automatically maintain and restore operation of the data communication network by loop connecting ones of the ring transmission paths together to isolate segments of the network experiencing trouble and to transfer maintenance and diagnostic data messages between ones of the looped ring transmission paths to restore ring transmission paths and nodes located in isolated segments of the network to service.
    Type: Grant
    Filed: October 11, 1984
    Date of Patent: July 28, 1987
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: David M. Rouse, Richard E. Wallace, Charles M. Zelms
  • Patent number: D488884
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: April 20, 2004
    Inventor: Richard E. Wallace