Patents by Inventor Richard E. Wallace

Richard E. Wallace has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12237223
    Abstract: Contact over active gate (COAG) structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A remnant of a di-block-co-polymer is over a portion of the plurality of gate structures or the plurality of conductive trench contact structures. An interlayer dielectric material is over the di-block-co-polymer, over the plurality of gate structures, and over the plurality of conductive trench contact structures. An opening in the interlayer dielectric material. A conductive structure is in the opening, the conductive structure in direct contact with a corresponding one of the trench contact structures or with a corresponding one of the gate contact structures.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: February 25, 2025
    Assignee: Intel Corporation
    Inventors: Paul A. Nyhus, Charles H. Wallace, Manish Chandhok, Mohit K Haran, Gurpreet Singh, Eungnak Han, Florian Gstrein, Richard E. Schenker, David Shykind, Jinnie Aloysius, Sean Pursel
  • Publication number: 20250046713
    Abstract: Self-aligned patterning with colored blocking and resulting structures are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate, and a hardmask layer on the ILD layer. A plurality of conductive interconnect lines is in and spaced apart by the ILD layer and the hardmask layer. The plurality of conductive interconnect lines includes a first interconnect line having a first width. A second interconnect line is immediately adjacent the first interconnect line by a first distance, the second interconnect line having the first width. A third interconnect line is immediately adjacent the second interconnect line by the first distance, the third interconnect line having the first width. A fourth interconnect line is immediately adjacent the third interconnect line by a second distance greater than the first distance, the fourth interconnect line having a second width greater than the first width.
    Type: Application
    Filed: October 21, 2024
    Publication date: February 6, 2025
    Inventors: Mohit K. HARAN, Reken PATEL, Richard E. SCHENKER, Charles H. WALLACE
  • Patent number: 12218052
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Grant
    Filed: October 27, 2023
    Date of Patent: February 4, 2025
    Assignee: Intel Corporation
    Inventors: Richard E. Schenker, Robert L Bristol, Kevin L. Lin, Florian Gstrein, James M. Blackwell, Marie Krysak, Manish Chandhok, Paul A Nyhus, Charles H. Wallace, Curtis W. Ward, Swaminathan Sivakumar, Elliot N. Tan
  • Publication number: 20040093683
    Abstract: A device is disclosed for controlling the operation of a vacuum cleaning assembly, which assembly includes a vacuum-creating source, a vacuum hose attachable to the vacuum-creating source, a vacuum cleaning head, and a suction wand operatively connecting the vacuum hose to the cleaning head. The device includes a wand connection member having a housing with a first end attachable to the vacuum hose and a second end attachable to the suction wand. A valve element is disposed in the housing. The valve element is movable between a closed position to block the vacuum between the vacuum-creating source and the cleaning head, and an open position to provide full vacuum between the vacuum-creating source and the cleaning head. A transfer mechanism is secured to the housing for controlling the movement of the valve element between its closed and open positions.
    Type: Application
    Filed: November 15, 2002
    Publication date: May 20, 2004
    Inventor: Richard E. Wallace
  • Patent number: 4860284
    Abstract: Apparatus and method for identifying the location of a lost token signal continuously transmitted on transmission paths interconnecting nodes of a network to sequentially enable the nodes to write data onto the network. The arrival of the token signal at each node is recorded in counter states of a token track counter corresponding with the node. The recorded binary counter states are compared upon the failure of the token signal to arrive at a node to detect mismatches and transitions occurring between adjacent nodes counter states identifying the network location of the lost token signal.
    Type: Grant
    Filed: April 20, 1988
    Date of Patent: August 22, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: David B. Brown, Richard E. Wallace
  • Patent number: 4752924
    Abstract: A data communication network comprising a plurality of nodes interconnecting transmission paths in a ring structure arranged to propagate data messages between data systems coupled to the network by the nodes in opposite directions around the network ring structure. An executive node having ring interface units interconnecting ones of the transmission paths is arranged to selectively couple a network control processor with various sectors of the transmission paths to enable the network control processor to control the traffic flow of data messages on the data communication network.
    Type: Grant
    Filed: September 5, 1985
    Date of Patent: June 21, 1988
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Joseph W. Darnell, Allen D. Fergeson, David M. Rouse, Richard E. Wallace, Charles M. Zelms
  • Patent number: 4683563
    Abstract: A data communication network comprising ring transmission paths (0,1) interconnecting ring interface nodes (RI1, RI2, RI3) coupled with a node processor and data systems and arranged to propagate data messages along the ring transmission paths between the data systems. Each node is arranged to detect failure of the node to propagate a data message to another node and to flush the data communication network by force reading data messages off the ring transmission paths into the blocked node processor. A node is arranged to automatically maintain and restore operation of the data communication network by loop connecting ones of the ring transmission paths together to isolate segments of the network experiencing trouble and to transfer maintenance and diagnostic data messages between ones of the looped ring transmission paths to restore ring transmission paths and nodes located in isolated segments of the network to service.
    Type: Grant
    Filed: October 11, 1984
    Date of Patent: July 28, 1987
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: David M. Rouse, Richard E. Wallace, Charles M. Zelms
  • Patent number: D488884
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: April 20, 2004
    Inventor: Richard E. Wallace