Patents by Inventor Richard Edward Serton

Richard Edward Serton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11803686
    Abstract: Provided are embodiments for a computer-implemented method for routing standard cells of an integrated circuit. Embodiments include obtaining a layout of a plurality of standard cells for routing, and determining existing output connections for each of the plurality of standard cells. Embodiments can also include generating a representation for the layout removing the existing output connections for each of the plurality of standard cells; and providing the representation of the layout to an autorouter. Also provided are embodiments for a system and computer program product for routing standard cells of an integrated circuit.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: October 31, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Richard Edward Serton
  • Patent number: 11663391
    Abstract: Aspects of the invention include systems and methods for implementing a CMOS circuit design that uses a sea-of-gates fill methodology to provide latch-up avoidance. A non-limiting example computer-implemented method includes identifying a fill cell in the circuit design. The fill cell can include a power rail, a ground rail, and a field-effect transistor (FET) electrically coupled to the power rail through a via. The method can include disconnecting the via from the power rail and moving the via to a disconnected node in the fill cell. Moving the via decouples a source or drain of the fill cell from a well of the fill cell, preventing latch-up while maintaining via and metal shape density.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: May 30, 2023
    Assignee: International Business Machines Corporation
    Inventors: David Wolpert, Ryan Michael Kruse, Leon Sigal, Richard Edward Serton, Matthew Stephen Angyal, Terence Hook, Richard Andre Wachnik
  • Publication number: 20230062945
    Abstract: Aspects of the invention include systems and methods for implementing a CMOS circuit design that uses a sea-of-gates fill methodology to provide latch-up avoidance. A non-limiting example computer-implemented method includes identifying a fill cell in the circuit design. The fill cell can include a power rail, a ground rail, and a field-effect transistor (FET) electrically coupled to the power rail through a via. The method can include disconnecting the via from the power rail and moving the via to a disconnected node in the fill cell. Moving the via decouples a source or drain of the fill cell from a well of the fill cell, preventing latch-up while maintaining via and metal shape density.
    Type: Application
    Filed: August 25, 2021
    Publication date: March 2, 2023
    Inventors: David Wolpert, Ryan Michael Kruse, Leon Sigal, Richard Edward Serton, Matthew Stephen Angyal, Terence Hook, Richard Andre Wachnik
  • Publication number: 20230047053
    Abstract: Provided are embodiments for a computer-implemented method for routing standard cells of an integrated circuit. Embodiments include obtaining a layout of a plurality of standard cells for routing, and determining existing output connections for each of the plurality of standard cells. Embodiments can also include generating a representation for the layout removing the existing output connections for each of the plurality of standard cells; and providing the representation of the layout to an autorouter. Also provided are embodiments for a system and computer program product for routing standard cells of an integrated circuit.
    Type: Application
    Filed: August 16, 2021
    Publication date: February 16, 2023
    Inventor: Richard Edward Serton